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drm/amdgpu: add emit_reg_write_reg_wait ring callback
This callback writes a value to a register and then reads back another register and waits for a value in a single operation. Provide a helper function using two operations for engines that don't support this opertion. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3 changed files with 28 additions and 0 deletions
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@ -1806,6 +1806,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
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#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
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#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
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#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
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#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
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#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
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#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
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@ -459,6 +459,26 @@ void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
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spin_unlock(&adev->ring_lru_list_lock);
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}
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/**
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* amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
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*
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* @adev: amdgpu_device pointer
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* @reg0: register to write
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* @reg1: register to wait on
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* @ref: reference value to write/wait on
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* @mask: mask to wait on
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*
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* Helper for rings that don't support write and wait in a
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* single oneshot packet.
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*/
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void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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{
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amdgpu_ring_emit_wreg(ring, reg0, ref);
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amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
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}
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/*
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* Debugfs info
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*/
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@ -154,6 +154,9 @@ struct amdgpu_ring_funcs {
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void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
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void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask);
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void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
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/* priority functions */
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void (*set_priority) (struct amdgpu_ring *ring,
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@ -228,6 +231,10 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
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int *blacklist, int num_blacklist,
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bool lru_pipe_order, struct amdgpu_ring **ring);
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void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t val0,
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uint32_t reg1, uint32_t val1);
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static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
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{
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int i = 0;
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