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drm/i915/display: Record the plane update times for debugging
Since we try and estimate how long we require to update the registers to
perform a plane update, it is of vital importance that we measure the
distribution of plane updates to better guide our estimate. If we
underestimate how long it takes to perform the plane update, we may
slip into the next scanout frame causing a tear. If we overestimate, we
may unnecessarily delay the update to the next frame, causing visible
jitter.
Replace the warning that we exceed some arbitrary threshold for the
vblank update with a histogram for debugfs.
v2: Add a per-crtc debugfs entry so that the information is easier to
extract when testing individual CRTC, and so that it can be reset before
a test.
v3: Flip the graph on its side; creates space to label the time axis.
Updates: 4684
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1us |
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4us |********
|**********
16us |***********
|*****
66us |
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262us |
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1ms |
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4ms |
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17ms |
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Min update: 5918ns
Max update: 54781ns
Average update: 16628ns
Overruns > 250us: 0
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1982
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #v2
Link: https://patchwork.freedesktop.org/patch/msgid/20201202212814.26320-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
54b3f0e681
commit
829270e455
6 changed files with 187 additions and 18 deletions
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@ -45,6 +45,7 @@
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#include "display/intel_crt.h"
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#include "display/intel_ddi.h"
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#include "display/intel_display_debugfs.h"
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#include "display/intel_dp.h"
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#include "display/intel_dp_mst.h"
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#include "display/intel_dpll_mgr.h"
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@ -17266,6 +17267,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
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return ERR_PTR(ret);
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}
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static int intel_crtc_late_register(struct drm_crtc *crtc)
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{
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intel_crtc_debugfs_add(crtc);
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return 0;
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}
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#define INTEL_CRTC_FUNCS \
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.gamma_set = drm_atomic_helper_legacy_gamma_set, \
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.set_config = drm_atomic_helper_set_config, \
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@ -17275,7 +17282,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
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.atomic_destroy_state = intel_crtc_destroy_state, \
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.set_crc_source = intel_crtc_set_crc_source, \
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.verify_crc_source = intel_crtc_verify_crc_source, \
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.get_crc_sources = intel_crtc_get_crc_sources
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.get_crc_sources = intel_crtc_get_crc_sources, \
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.late_register = intel_crtc_late_register
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static const struct drm_crtc_funcs bdw_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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@ -18,6 +18,7 @@
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_sideband.h"
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#include "intel_sprite.h"
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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
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{
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@ -865,6 +866,110 @@ static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
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}
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
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static void crtc_updates_info(struct seq_file *m,
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struct intel_crtc *crtc,
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const char *hdr)
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{
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u64 count;
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int row;
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count = 0;
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for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++)
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count += crtc->debug.vbl.times[row];
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seq_printf(m, "%sUpdates: %llu\n", hdr, count);
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if (!count)
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return;
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for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) {
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char columns[80] = " |";
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unsigned int x;
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if (row & 1) {
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const char *units;
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if (row > 10) {
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x = 1000000;
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units = "ms";
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} else {
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x = 1000;
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units = "us";
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}
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snprintf(columns, sizeof(columns), "%4ld%s |",
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DIV_ROUND_CLOSEST(BIT(row + 9), x), units);
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}
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if (crtc->debug.vbl.times[row]) {
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x = ilog2(crtc->debug.vbl.times[row]);
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memset(columns + 8, '*', x);
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columns[8 + x] = '\0';
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}
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seq_printf(m, "%s%s\n", hdr, columns);
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}
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seq_printf(m, "%sMin update: %lluns\n",
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hdr, crtc->debug.vbl.min);
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seq_printf(m, "%sMax update: %lluns\n",
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hdr, crtc->debug.vbl.max);
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seq_printf(m, "%sAverage update: %lluns\n",
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hdr, div64_u64(crtc->debug.vbl.sum, count));
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seq_printf(m, "%sOverruns > %uus: %u\n",
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hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
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}
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static int crtc_updates_show(struct seq_file *m, void *data)
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{
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crtc_updates_info(m, m->private, "");
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return 0;
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}
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static int crtc_updates_open(struct inode *inode, struct file *file)
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{
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return single_open(file, crtc_updates_show, inode->i_private);
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}
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static ssize_t crtc_updates_write(struct file *file,
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const char __user *ubuf,
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size_t len, loff_t *offp)
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{
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struct seq_file *m = file->private_data;
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struct intel_crtc *crtc = m->private;
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/* May race with an update. Meh. */
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memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl));
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return len;
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}
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static const struct file_operations crtc_updates_fops = {
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.owner = THIS_MODULE,
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.open = crtc_updates_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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.write = crtc_updates_write
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};
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static void crtc_updates_add(struct drm_crtc *crtc)
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{
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debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry,
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to_intel_crtc(crtc), &crtc_updates_fops);
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}
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#else
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static void crtc_updates_info(struct seq_file *m,
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struct intel_crtc *crtc,
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const char *hdr)
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{
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}
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static void crtc_updates_add(struct drm_crtc *crtc)
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{
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}
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#endif
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static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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@ -907,6 +1012,8 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
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seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n",
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yesno(!crtc->cpu_fifo_underrun_disabled),
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yesno(!crtc->pch_fifo_underrun_disabled));
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crtc_updates_info(m, crtc, "\t");
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}
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static int i915_display_info(struct seq_file *m, void *unused)
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@ -2278,3 +2385,20 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
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return 0;
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}
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/**
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* intel_crtc_debugfs_add - add i915 specific crtc debugfs files
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* @crtc: pointer to a drm_crtc
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*
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* Returns 0 on success, negative error codes on error.
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*
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* Failure to add debugfs entries should generally be ignored.
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*/
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int intel_crtc_debugfs_add(struct drm_crtc *crtc)
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{
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if (!crtc->debugfs_entry)
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return -ENODEV;
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crtc_updates_add(crtc);
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return 0;
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}
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@ -7,14 +7,17 @@
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#define __INTEL_DISPLAY_DEBUGFS_H__
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struct drm_connector;
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struct drm_crtc;
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struct drm_i915_private;
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#ifdef CONFIG_DEBUG_FS
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void intel_display_debugfs_register(struct drm_i915_private *i915);
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int intel_connector_debugfs_add(struct drm_connector *connector);
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int intel_crtc_debugfs_add(struct drm_crtc *crtc);
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#else
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static inline void intel_display_debugfs_register(struct drm_i915_private *i915) {}
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static inline int intel_connector_debugfs_add(struct drm_connector *connector) { return 0; }
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static inline int intel_crtc_debugfs_add(struct drm_crtc *crtc) { return 0; }
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#endif
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#endif /* __INTEL_DISPLAY_DEBUGFS_H__ */
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@ -1188,6 +1188,15 @@ struct intel_crtc {
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ktime_t start_vbl_time;
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int min_vbl, max_vbl;
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int scanline_start;
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#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
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struct {
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u64 min;
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u64 max;
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u64 sum;
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unsigned int over;
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unsigned int times[17]; /* [1us, 16ms] */
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} vbl;
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#endif
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} debug;
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/* scalers available on this crtc */
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@ -61,14 +61,6 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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1000 * adjusted_mode->crtc_htotal);
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}
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/* FIXME: We should instead only take spinlocks once for the entire update
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* instead of once per mmio. */
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#if IS_ENABLED(CONFIG_PROVE_LOCKING)
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#define VBLANK_EVASION_TIME_US 250
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#else
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#define VBLANK_EVASION_TIME_US 100
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#endif
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/**
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* intel_pipe_update_start() - start update of a set of display registers
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* @new_crtc_state: the new crtc state
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@ -187,6 +179,36 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
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local_irq_disable();
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
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static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end)
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{
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u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time));
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unsigned int h;
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h = ilog2(delta >> 9);
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if (h >= ARRAY_SIZE(crtc->debug.vbl.times))
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h = ARRAY_SIZE(crtc->debug.vbl.times) - 1;
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crtc->debug.vbl.times[h]++;
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crtc->debug.vbl.sum += delta;
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if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min)
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crtc->debug.vbl.min = delta;
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if (delta > crtc->debug.vbl.max)
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crtc->debug.vbl.max = delta;
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if (delta > 1000 * VBLANK_EVASION_TIME_US) {
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drm_dbg_kms(crtc->base.dev,
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"Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
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pipe_name(crtc->pipe),
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div_u64(delta, 1000),
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VBLANK_EVASION_TIME_US);
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crtc->debug.vbl.over++;
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}
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}
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#else
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static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
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#endif
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/**
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* intel_pipe_update_end() - end update of a set of display registers
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* @new_crtc_state: the new crtc state
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@ -249,15 +271,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
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crtc->debug.min_vbl, crtc->debug.max_vbl,
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crtc->debug.scanline_start, scanline_end);
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}
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#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
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else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
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VBLANK_EVASION_TIME_US)
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drm_warn(&dev_priv->drm,
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"Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
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pipe_name(pipe),
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ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
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VBLANK_EVASION_TIME_US);
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#endif
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dbg_vblank_evade(crtc, end_vbl_time);
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}
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int intel_plane_check_stride(const struct intel_plane_state *plane_state)
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@ -17,6 +17,16 @@ struct drm_i915_private;
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struct intel_crtc_state;
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struct intel_plane_state;
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/*
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* FIXME: We should instead only take spinlocks once for the entire update
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* instead of once per mmio.
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*/
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#if IS_ENABLED(CONFIG_PROVE_LOCKING)
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#define VBLANK_EVASION_TIME_US 250
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#else
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#define VBLANK_EVASION_TIME_US 100
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#endif
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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs);
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struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
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