ARM: cache: remove ARMv3 support code
This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Acked-by: Hyok S. Choi <hyok.choi@samsung.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
4cc3daaf39
commit
82d9b0d0c6
|
|
@ -19,14 +19,6 @@
|
|||
#undef _CACHE
|
||||
#undef MULTI_CACHE
|
||||
|
||||
#if defined(CONFIG_CPU_CACHE_V3)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
# define _CACHE v3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_CACHE_V4)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ config CPU_ARM740T
|
|||
depends on !MMU
|
||||
select CPU_32v4T
|
||||
select CPU_ABRT_LV4T
|
||||
select CPU_CACHE_V3 # although the core is v4t
|
||||
select CPU_CACHE_V4
|
||||
select CPU_CP15_MPU
|
||||
select CPU_PABRT_LEGACY
|
||||
help
|
||||
|
|
@ -469,9 +469,6 @@ config CPU_PABRT_V7
|
|||
bool
|
||||
|
||||
# The cache model
|
||||
config CPU_CACHE_V3
|
||||
bool
|
||||
|
||||
config CPU_CACHE_V4
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@ obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
|
|||
obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
|
||||
obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
|
||||
|
||||
obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o
|
||||
obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
|
||||
obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
|
||||
obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
|
||||
|
|
|
|||
|
|
@ -1,137 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mm/cache-v3.S
|
||||
*
|
||||
* Copyright (C) 1997-2002 Russell king
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/page.h>
|
||||
#include "proc-macros.S"
|
||||
|
||||
/*
|
||||
* flush_icache_all()
|
||||
*
|
||||
* Unconditionally clean and invalidate the entire icache.
|
||||
*/
|
||||
ENTRY(v3_flush_icache_all)
|
||||
mov pc, lr
|
||||
ENDPROC(v3_flush_icache_all)
|
||||
|
||||
/*
|
||||
* flush_user_cache_all()
|
||||
*
|
||||
* Invalidate all cache entries in a particular address
|
||||
* space.
|
||||
*
|
||||
* - mm - mm_struct describing address space
|
||||
*/
|
||||
ENTRY(v3_flush_user_cache_all)
|
||||
/* FALLTHROUGH */
|
||||
/*
|
||||
* flush_kern_cache_all()
|
||||
*
|
||||
* Clean and invalidate the entire cache.
|
||||
*/
|
||||
ENTRY(v3_flush_kern_cache_all)
|
||||
/* FALLTHROUGH */
|
||||
|
||||
/*
|
||||
* flush_user_cache_range(start, end, flags)
|
||||
*
|
||||
* Invalidate a range of cache entries in the specified
|
||||
* address space.
|
||||
*
|
||||
* - start - start address (may not be aligned)
|
||||
* - end - end address (exclusive, may not be aligned)
|
||||
* - flags - vma_area_struct flags describing address space
|
||||
*/
|
||||
ENTRY(v3_flush_user_cache_range)
|
||||
mov ip, #0
|
||||
mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* coherent_kern_range(start, end)
|
||||
*
|
||||
* Ensure coherency between the Icache and the Dcache in the
|
||||
* region described by start. If you have non-snooping
|
||||
* Harvard caches, you need to implement this function.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*/
|
||||
ENTRY(v3_coherent_kern_range)
|
||||
/* FALLTHROUGH */
|
||||
|
||||
/*
|
||||
* coherent_user_range(start, end)
|
||||
*
|
||||
* Ensure coherency between the Icache and the Dcache in the
|
||||
* region described by start. If you have non-snooping
|
||||
* Harvard caches, you need to implement this function.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*/
|
||||
ENTRY(v3_coherent_user_range)
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* flush_kern_dcache_area(void *page, size_t size)
|
||||
*
|
||||
* Ensure no D cache aliasing occurs, either with itself or
|
||||
* the I cache
|
||||
*
|
||||
* - addr - kernel address
|
||||
* - size - region size
|
||||
*/
|
||||
ENTRY(v3_flush_kern_dcache_area)
|
||||
/* FALLTHROUGH */
|
||||
|
||||
/*
|
||||
* dma_flush_range(start, end)
|
||||
*
|
||||
* Clean and invalidate the specified virtual address range.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*/
|
||||
ENTRY(v3_dma_flush_range)
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* dma_unmap_area(start, size, dir)
|
||||
* - start - kernel virtual start address
|
||||
* - size - size of region
|
||||
* - dir - DMA direction
|
||||
*/
|
||||
ENTRY(v3_dma_unmap_area)
|
||||
teq r2, #DMA_TO_DEVICE
|
||||
bne v3_dma_flush_range
|
||||
/* FALLTHROUGH */
|
||||
|
||||
/*
|
||||
* dma_map_area(start, size, dir)
|
||||
* - start - kernel virtual start address
|
||||
* - size - size of region
|
||||
* - dir - DMA direction
|
||||
*/
|
||||
ENTRY(v3_dma_map_area)
|
||||
mov pc, lr
|
||||
ENDPROC(v3_dma_unmap_area)
|
||||
ENDPROC(v3_dma_map_area)
|
||||
|
||||
.globl v3_flush_kern_cache_louis
|
||||
.equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
|
||||
|
||||
__INITDATA
|
||||
|
||||
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
|
||||
define_cache_functions v3
|
||||
|
|
@ -145,5 +145,5 @@ __arm740_proc_info:
|
|||
.long arm740_processor_functions
|
||||
.long 0
|
||||
.long 0
|
||||
.long v3_cache_fns @ cache model
|
||||
.long v4_cache_fns @ cache model
|
||||
.size __arm740_proc_info, . - __arm740_proc_info
|
||||
|
|
|
|||
Loading…
Reference in New Issue