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perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints
[ Upstream commit23e3983a46
] This patch fixes an bug revealed by the following commit:6b89d4c1ae
("perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking") That patch modified INTEL_FLAGS_EVENT_CONSTRAINT() to only look at the event code when matching a constraint. If code+umask were needed, then the INTEL_FLAGS_UEVENT_CONSTRAINT() macro was needed instead. This broke with some of the constraints for PEBS events. Several of them, including the one used for cycles:p, cycles:pp, cycles:ppp fell in that category and caused the event to be rejected in PEBS mode. In other words, on some platforms a cmdline such as: $ perf top -e cycles:pp would fail with -EINVAL. This patch fixes this bug by properly using INTEL_FLAGS_UEVENT_CONSTRAINT() when needed in the PEBS constraint tables. Reported-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Stephane Eranian <eranian@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: kan.liang@intel.com Link: http://lkml.kernel.org/r/20190521005246.423-1-eranian@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
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commit
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1 changed files with 14 additions and 14 deletions
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@ -681,7 +681,7 @@ struct event_constraint intel_core2_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
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INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
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/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
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EVENT_CONSTRAINT_END
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};
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@ -690,7 +690,7 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
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INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
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/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
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EVENT_CONSTRAINT_END
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@ -698,7 +698,7 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
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struct event_constraint intel_slm_pebs_event_constraints[] = {
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/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
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EVENT_CONSTRAINT_END
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@ -729,7 +729,7 @@ struct event_constraint intel_nehalem_pebs_event_constraints[] = {
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INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
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/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
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EVENT_CONSTRAINT_END
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};
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@ -746,7 +746,7 @@ struct event_constraint intel_westmere_pebs_event_constraints[] = {
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INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
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/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
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EVENT_CONSTRAINT_END
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};
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@ -755,7 +755,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
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INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
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INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
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@ -770,9 +770,9 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
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INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
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INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
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/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
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@ -786,9 +786,9 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
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INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
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/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
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@ -809,9 +809,9 @@ struct event_constraint intel_bdw_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
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INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
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/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
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@ -832,9 +832,9 @@ struct event_constraint intel_bdw_pebs_event_constraints[] = {
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struct event_constraint intel_skl_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
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/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
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/* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
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INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
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