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intel_rapl: remove hardcoded register index
enum rapl_domain_reg_id is defined for the RAPL registers for each RAPL domain, thus use it whenever possible. Reviewed-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Tested-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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parent
f7c4e0c89b
commit
8310e8202f
1 changed files with 22 additions and 22 deletions
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@ -642,11 +642,11 @@ static void rapl_init_domains(struct rapl_package *rp)
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case BIT(RAPL_DOMAIN_PACKAGE):
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rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
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rd->id = RAPL_DOMAIN_PACKAGE;
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rd->regs[0] = MSR_PKG_POWER_LIMIT;
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rd->regs[1] = MSR_PKG_ENERGY_STATUS;
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rd->regs[2] = MSR_PKG_PERF_STATUS;
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rd->regs[3] = 0;
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rd->regs[4] = MSR_PKG_POWER_INFO;
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rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PKG_POWER_LIMIT;
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rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PKG_ENERGY_STATUS;
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rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_PKG_PERF_STATUS;
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rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
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rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_PKG_POWER_INFO;
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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rd->rpl[1].prim_id = PL2_ENABLE;
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@ -655,33 +655,33 @@ static void rapl_init_domains(struct rapl_package *rp)
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case BIT(RAPL_DOMAIN_PP0):
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rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
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rd->id = RAPL_DOMAIN_PP0;
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rd->regs[0] = MSR_PP0_POWER_LIMIT;
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rd->regs[1] = MSR_PP0_ENERGY_STATUS;
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rd->regs[2] = 0;
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rd->regs[3] = MSR_PP0_POLICY;
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rd->regs[4] = 0;
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rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP0_POWER_LIMIT;
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rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP0_ENERGY_STATUS;
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rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
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rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP0_POLICY;
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rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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break;
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case BIT(RAPL_DOMAIN_PP1):
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rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
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rd->id = RAPL_DOMAIN_PP1;
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rd->regs[0] = MSR_PP1_POWER_LIMIT;
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rd->regs[1] = MSR_PP1_ENERGY_STATUS;
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rd->regs[2] = 0;
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rd->regs[3] = MSR_PP1_POLICY;
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rd->regs[4] = 0;
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rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP1_POWER_LIMIT;
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rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP1_ENERGY_STATUS;
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rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
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rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP1_POLICY;
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rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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break;
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case BIT(RAPL_DOMAIN_DRAM):
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rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
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rd->id = RAPL_DOMAIN_DRAM;
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rd->regs[0] = MSR_DRAM_POWER_LIMIT;
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rd->regs[1] = MSR_DRAM_ENERGY_STATUS;
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rd->regs[2] = MSR_DRAM_PERF_STATUS;
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rd->regs[3] = 0;
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rd->regs[4] = MSR_DRAM_POWER_INFO;
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rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_DRAM_POWER_LIMIT;
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rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_DRAM_ENERGY_STATUS;
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rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_DRAM_PERF_STATUS;
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rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
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rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_DRAM_POWER_INFO;
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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rd->domain_energy_unit =
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@ -1282,8 +1282,8 @@ static int __init rapl_register_psys(void)
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rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
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rd->id = RAPL_DOMAIN_PLATFORM;
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rd->regs[0] = MSR_PLATFORM_POWER_LIMIT;
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rd->regs[1] = MSR_PLATFORM_ENERGY_STATUS;
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rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PLATFORM_POWER_LIMIT;
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rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PLATFORM_ENERGY_STATUS;
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rd->rpl[0].prim_id = PL1_ENABLE;
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rd->rpl[0].name = pl1_name;
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rd->rpl[1].prim_id = PL2_ENABLE;
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