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MIPS updates for v5.11: 

- enabled GCOV
 - reworked setup of protection map
 - added support for more MSCC platforms
 - added sysfs boardinfo for Loongson64
 - enabled KASLR for Loogson64
 - added reset controller for BCM63xx
 - cleanups and fixes
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Merge tag 'mips_5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - enable GCOV

 - rework setup of protection map

 - add support for more MSCC platforms

 - add sysfs boardinfo for Loongson64

 - enable KASLR for Loogson64

 - add reset controller for BCM63xx

 - cleanups and fixes

* tag 'mips_5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (70 commits)
  mips: fix Section mismatch in reference
  MAINTAINERS: Add linux-mips mailing list to JZ47xx entries
  MAINTAINERS: Remove JZ4780 DMA driver entry
  MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org
  MIPS: Octeon: irq: Alloc desc before configuring IRQ
  MIPS: mm: Add back define for PAGE_SHARED
  MIPS: Select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL to enable sysfs memblock debug
  mips: lib: uncached: fix non-standard usage of variable 'sp'
  MIPS: DTS: img: Fix schema warnings for pwm-leds
  MIPS: KASLR: Avoid endless loop in sync_icache if synci_step is zero
  MIPS: Move memblock_dump_all() to the end of setup_arch()
  MIPS: SMP-CPS: Add support for irq migration when CPU offline
  MIPS: OCTEON: Don't add kernel sections into memblock allocator
  MIPS: Don't round up kernel sections size for memblock_add()
  MIPS: Enable GCOV
  MIPS: configs: drop unused BACKLIGHT_GENERIC option
  MIPS: Loongson64: Fix up reserving kernel memory range
  MIPS: mm: Remove unused is_aligned_hugepage_range
  MIPS: No need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable()
  mips: cdmm: fix use-after-free in mips_cdmm_bus_discover
  ...
This commit is contained in:
Linus Torvalds 2020-12-16 12:07:54 -08:00
parent 66fc6a6254 ad4fddef5f
commit 8312f41f08
94 changed files with 2329 additions and 279 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.mailmap
View File

@ -122,6 +122,8 @@ Henk Vergonet <Henk.Vergonet@gmail.com>
Henrik Kretzschmar <henne@nachtwindheim.de>
Henrik Rydberg <rydberg@bitmath.org>
Herbert Xu <herbert@gondor.apana.org.au>
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
Jacob Shin <Jacob.Shin@amd.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>

35
Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo Normal file
View File

@ -0,0 +1,35 @@
What: /sys/firmware/lefi/boardinfo
Date: October 2020
Contact: Tiezhu Yang <yangtiezhu@loongson.cn>
Description:
Get mainboard and BIOS info easily on the Loongson platform,
this is useful to point out the current used mainboard type
and BIOS version when there exists problems related with
hardware or firmware.
The related structures are already defined in the interface
specification about firmware and kernel which are common
requirement and specific for Loongson64, so only add a new
boardinfo.c file in arch/mips/loongson64.
For example:
[loongson@linux ~]$ cat /sys/firmware/lefi/boardinfo
Board Info
Manufacturer : LEMOTE
Board Name : LEMOTE-LS3A4000-7A1000-1w-V01-pc
Family : LOONGSON3
BIOS Info
Vendor : Kunlun
Version : Kunlun-A1901-V4.1.3-20200414093938
ROM Size : 4 KB
Release Date : 2020-04-14
By the way, using dmidecode command can get the similar info if there
exists SMBIOS in firmware, but the fact is that there is no SMBIOS on
some machines, we can see nothing when execute dmidecode, like this:
[root@linux loongson]# dmidecode
# dmidecode 2.12
# No SMBIOS nor DMI entry point found, sorry.

2
Documentation/devicetree/bindings/mips/mscc.txt
View File

@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
- compatible: "mscc,ocelot"
- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
* Other peripherals:

37
Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml Normal file
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: BCM6345 reset controller
description: This document describes the BCM6345 reset controller.
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
properties:
compatible:
const: brcm,bcm6345-reset
reg:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};

11
MAINTAINERS
View File

@ -8736,19 +8736,16 @@ F: include/uapi/rdma/
F: samples/bpf/ibumad_kern.c
F: samples/bpf/ibumad_user.c
INGENIC JZ4780 DMA Driver
M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
S: Maintained
F: drivers/dma/dma-jz4780.c
INGENIC JZ4780 NAND DRIVER
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mtd@lists.infradead.org
L: linux-mips@vger.kernel.org
S: Maintained
F: drivers/mtd/nand/raw/ingenic/
INGENIC JZ47xx SoCs
M: Paul Cercueil <paul@crapouillou.net>
L: linux-mips@vger.kernel.org
S: Maintained
F: arch/mips/boot/dts/ingenic/
F: arch/mips/generic/board-ingenic.c
@ -9710,7 +9707,7 @@ F: arch/arm64/kvm/
F: include/kvm/arm_*
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
M: Huacai Chen <chenhc@lemote.com>
M: Huacai Chen <chenhuacai@kernel.org>
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
L: linux-mips@vger.kernel.org
L: kvm@vger.kernel.org
@ -11852,7 +11849,7 @@ F: drivers/*/*/*loongson2*
F: drivers/*/*loongson2*
MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <chenhc@lemote.com>
M: Huacai Chen <chenhuacai@kernel.org>
M: Jiaxun Yang <jiaxun.yang@flygoat.com>
L: linux-mips@vger.kernel.org
S: Maintained

15
arch/mips/Kconfig
View File

@ -9,6 +9,8 @@ config MIPS
select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN_SANITIZE_ALL
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL
select ARCH_SUPPORTS_UPROBES
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
@ -248,6 +250,7 @@ config ATH79
config BMIPS_GENERIC
bool "Broadcom Generic BMIPS kernel"
select ARCH_HAS_RESET_CONTROLLER
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
select ARCH_HAS_PHYS_TO_DMA
select BOOT_RAW
@ -486,6 +489,7 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_RELOCATABLE
select ZONE_DMA32
select NUMA
select SMP
@ -2484,6 +2488,7 @@ config MIPS_CPS
select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
select SYS_SUPPORTS_SMP
select WEAK_ORDERING
select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
help
Select this if you wish to run an SMP kernel across multiple cores
within a MIPS Coherent Processing System. When this option is
@ -2644,7 +2649,7 @@ config WAR_R4600_V1_INDEX_ICACHEOP
# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
# executed if there is no other dcache activity. If the dcache is
# accessed for another instruction immeidately preceding when these
# accessed for another instruction immediately preceding when these
# cache instructions are executing, it is possible that the dcache
# tag match outputs used by these cache instructions will be
# incorrect. These cache instructions should be preceded by at least
@ -2777,7 +2782,8 @@ config RELOCATABLE
depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
CPU_P5600 || CAVIUM_OCTEON_SOC
CPU_P5600 || CAVIUM_OCTEON_SOC || \
CPU_LOONGSON64
help
This builds a kernel image that retains relocation information
so it can be loaded someplace besides the default 1MB.
@ -2788,6 +2794,7 @@ config RELOCATION_TABLE_SIZE
hex "Relocation table size"
depends on RELOCATABLE
range 0x0 0x01000000
default "0x00200000" if CPU_LOONGSON64
default "0x00100000"
help
A table of relocation data will be appended to the kernel binary
@ -3086,7 +3093,7 @@ config MIPS_O32_FP64_SUPPORT
Although binutils currently supports use of this flag the details
concerning its effect upon the O32 ABI in userland are still being
worked on. In order to avoid userland becoming dependant upon current
worked on. In order to avoid userland becoming dependent upon current
behaviour before the details have been finalised, this option should
be considered experimental and only enabled by those working upon
said details.
@ -3124,7 +3131,7 @@ choice
objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
This is meant as a backward compatiblity convenience for those
This is meant as a backward compatibility convenience for those
systems with a bootloader that can't be upgraded to accommodate
the documented boot protocol using a device tree.

3
arch/mips/Makefile
View File

@ -347,6 +347,7 @@ bootz-y += vmlinuz.srec
ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0)
bootz-y += uzImage.bin
endif
bootz-y += vmlinuz.itb
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
@ -378,7 +379,7 @@ ifdef CONFIG_SYS_SUPPORTS_ZBOOT
# boot/compressed
$(bootz-y): $(vmlinux-32) FORCE
$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
$(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
$(bootvars-y) 32bit-bfd=$(32bit-bfd) arch/mips/boot/$@
else
vmlinuz: FORCE
@echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled'

1
arch/mips/ar7/gpio.c
View File

@ -319,6 +319,7 @@ int __init ar7_gpio_init(void)
if (ret) {
printk(KERN_ERR "%s: failed to add gpiochip\n",
gpch->chip.label);
iounmap(gpch->regs);
return ret;
}
printk(KERN_INFO "%s: registered %d GPIOs\n",

2
arch/mips/bcm47xx/Kconfig
View File

@ -9,6 +9,7 @@ config BCM47XX_SSB
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
select SSB_PCIHOST if PCI
select SSB_B43_PCI_BRIDGE if PCI
select SSB_DRIVER_PCICORE if PCI
select SSB_PCICORE_HOSTMODE if PCI
@ -27,6 +28,7 @@ config BCM47XX_BCMA
select BCMA
select BCMA_HOST_SOC
select BCMA_DRIVER_MIPS
select BCMA_DRIVER_PCI if PCI
select BCMA_DRIVER_PCI_HOSTMODE if PCI
select BCMA_DRIVER_GPIO
default y

1
arch/mips/boot/.gitignore vendored
View File

@ -2,6 +2,7 @@
mkboot
elf2ecoff
vmlinux.*
vmlinuz.*
zImage
zImage.tmp
calc_vmlinuz_load_addr

97
arch/mips/boot/compressed/Makefile
View File

@ -36,6 +36,7 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in.
KCOV_INSTRUMENT := n
GCOV_PROFILE := n
# decompressor objects (linked with vmlinuz)
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o
@ -65,7 +66,9 @@ $(obj)/bswapsi.c: $(obj)/%.c: $(srctree)/arch/mips/lib/%.c FORCE
targets := $(notdir $(vmlinuzobjs-y))
targets += vmlinux.bin
OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
$(call if_changed,objcopy)
@ -78,12 +81,15 @@ tool_$(CONFIG_KERNEL_XZ) = xzkern
tool_$(CONFIG_KERNEL_ZSTD) = zstd22
targets += vmlinux.bin.z
$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
$(call if_changed,$(tool_y))
targets += piggy.o dummy.o
OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
--set-section-flags=.image=contents,alloc,load,readonly,data
$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
$(call if_changed,objcopy)
@ -102,14 +108,21 @@ UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS)
vmlinuzobjs-y += $(obj)/piggy.o
targets += ../../../../vmlinuz
quiet_cmd_zld = LD $@
cmd_zld = $(LD) $(KBUILD_LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
quiet_cmd_strip = STRIP $@
quiet_cmd_strip = STRIP $@
cmd_strip = $(STRIP) -s $@
vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
$(objtree)/vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
$(call cmd,zld)
$(call cmd,strip)
objboot := $(objtree)/arch/mips/boot
$(objboot)/vmlinuz: $(objtree)/vmlinuz FORCE
#
# Some DECstations need all possible sections of an ECOFF executable
#
@ -121,34 +134,90 @@ endif
hostprogs += ../elf2ecoff
ifdef CONFIG_32BIT
VMLINUZ = vmlinuz
VMLINUZ = $(objtree)/vmlinuz
else
VMLINUZ = vmlinuz.32
VMLINUZ = $(objboot)/vmlinuz.32
endif
targets += ../vmlinuz.32
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinuz.32: vmlinuz
$(objboot)/vmlinuz.32: $(objtree)/vmlinuz
$(call cmd,32)
targets += ../vmlinuz.ecoff
quiet_cmd_ecoff = ECOFF $@
cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
$(objboot)/vmlinuz.ecoff: $(objboot)/elf2ecoff $(VMLINUZ)
$(call cmd,ecoff)
targets += ../vmlinuz.bin
OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
vmlinuz.bin: vmlinuz
$(objboot)/vmlinuz.bin: $(objtree)/vmlinuz
$(call cmd,objcopy)
targets += ../vmlinuz.srec
OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
vmlinuz.srec: vmlinuz
$(objboot)/vmlinuz.srec: $(objtree)/vmlinuz
$(call cmd,objcopy)
uzImage.bin: vmlinuz.bin FORCE
targets += ../uzImage.bin
$(objboot)/uzImage.bin: $(objboot)/vmlinuz.bin FORCE
$(call if_changed,uimage,none)
clean-files += $(objtree)/vmlinuz
clean-files += $(objtree)/vmlinuz.32
clean-files += $(objtree)/vmlinuz.ecoff
clean-files += $(objtree)/vmlinuz.bin
clean-files += $(objtree)/vmlinuz.srec
#
# Flattened Image Tree (.itb) image
#
ifeq ($(ADDR_BITS),32)
itb_addr_cells = 1
endif
ifeq ($(ADDR_BITS),64)
itb_addr_cells = 2
endif
targets += ../vmlinuz.its.S
quiet_cmd_its_cat = CAT $@
cmd_its_cat = cat $(real-prereqs) >$@
$(objboot)/vmlinuz.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) FORCE
$(call if_changed,its_cat)
targets += ../vmlinuz.its
quiet_cmd_cpp_its_S = ITS $@
cmd_cpp_its_S = $(CPP) -P -C -o $@ $< \
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
-DVMLINUX_BINARY="\"$(2)\"" \
-DVMLINUX_COMPRESSION="\"none\"" \
-DVMLINUX_LOAD_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) \
-DVMLINUX_ENTRY_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) \
-DADDR_BITS=$(ADDR_BITS) \
-DADDR_CELLS=$(itb_addr_cells)
$(objboot)/vmlinuz.its: $(objboot)/vmlinuz.its.S FORCE
$(call if_changed,cpp_its_S,vmlinuz.bin)
targets += ../vmlinuz.itb
quiet_cmd_itb-image = ITB $@
cmd_itb-image = \
env PATH="$(objtree)/scripts/dtc:$(PATH)" \
$(BASH) $(MKIMAGE) \
-D "-I dts -O dtb -p 500 \
--include $(objtree)/arch/mips \
--warning no-unit_address_vs_reg" \
-f $(2) $@
$(objboot)/vmlinuz.itb: $(objboot)/vmlinuz.its $(objboot)/vmlinuz.bin FORCE
$(call if_changed,itb-image,$<)

9
arch/mips/boot/compressed/ld.script
View File

@ -31,9 +31,12 @@ SECTIONS
CONSTRUCTORS
. = ALIGN(16);
}
__appended_dtb = .;
/* leave space for appended DTB */
. += 0x100000;
.appended_dtb : {
__appended_dtb = .;
/* leave space for appended DTB */
. += 0x100000;
}
_edata = .;
/* End of data section */

2
arch/mips/boot/dts/Makefile
View File

@ -6,7 +6,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
subdir-$(CONFIG_MACH_INGENIC) += ingenic
subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
subdir-$(CONFIG_MSCC_OCELOT) += mscc
subdir-$(CONFIG_SOC_VCOREIII) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic

6
arch/mips/boot/dts/brcm/bcm63268.dtsi
View File

@ -70,6 +70,12 @@
mask = <0x1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,

6
arch/mips/boot/dts/brcm/bcm6328.dtsi
View File

@ -57,6 +57,12 @@
#clock-cells = <1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,

6
arch/mips/boot/dts/brcm/bcm6358.dtsi
View File

@ -82,6 +82,12 @@
interrupts = <2>, <3>;
};
periph_rst: reset-controller@fffe0034 {
compatible = "brcm,bcm6345-reset";
reg = <0xfffe0034 0x4>;
#reset-cells = <1>;
};
leds0: led-controller@fffe00d0 {
#address-cells = <1>;
#size-cells = <0>;

6
arch/mips/boot/dts/brcm/bcm6362.dtsi
View File

@ -70,6 +70,12 @@
mask = <0x1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,

6
arch/mips/boot/dts/brcm/bcm6368.dtsi
View File

@ -70,6 +70,12 @@
mask = <0x1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,

5
arch/mips/boot/dts/img/pistachio_marduk.dts
View File

@ -46,9 +46,10 @@
regulator-max-microvolt = <1800000>;
};
leds {
led-controller {
compatible = "pwm-leds";
heartbeat {
led-1 {
label = "marduk:red:heartbeat";
pwms = <&pwm 3 300000>;
max-brightness = <255>;

45
arch/mips/boot/dts/ingenic/ci20.dts
View File

@ -69,9 +69,11 @@
eth0_power: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "eth0_power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
enable-active-high;
};
@ -83,16 +85,39 @@
wlan0_power: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan0_power";
gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
enable-active-high;
};
otg_power: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "otg_power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
enable-active-high;
};
};
&ext {
clock-frequency = <48000000>;
};
&cgu {
/*
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
assigned-clock-rates = <48000000>;
};
&mmc0 {
status = "okay";
@ -396,6 +421,16 @@
status = "okay";
};
&otg_phy {
status = "okay";
vcc-supply = <&otg_power>;
};
&otg {
status = "okay";
};
&pinctrl {
pins_uart0: uart0 {
function = "uart0";
@ -489,7 +524,11 @@
};
&tcu {
/* 3 MHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
assigned-clock-rates = <3000000>, <3000000>;
/*
* 750 kHz for the system timer and 3 MHz for the clocksource,
* use channel #0 for the system timer, #1 for the clocksource.
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_OST>;
assigned-clock-rates = <750000>, <3000000>, <3000000>;
};

64
arch/mips/boot/dts/ingenic/cu1000-neo.dts
View File

@ -3,7 +3,7 @@
#include "x1000.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/clock/ingenic,sysost.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@ -31,6 +31,42 @@
};
};
ssi: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;
mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
status = "okay";
spi-max-frequency = <50000000>;
sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */
spi-max-frequency = <4000000>;
clocks = <&exclk_sc16is752>;
interrupt-parent = <&gpc>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@ -43,13 +79,19 @@
clock-frequency = <24000000>;
};
&tcu {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
assigned-clock-rates = <1500000>, <1500000>;
&cgu {
/*
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks = <&cgu X1000_CLK_RTC>;
assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
};
/* Use channel #0 for the system timer channel #2 for the clocksource */
ingenic,pwm-channels-mask = <0xfa>;
&ost {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
&uart2 {
@ -135,6 +177,14 @@
};
};
&otg_phy {
status = "okay";
};
&otg {
status = "okay";
};
&pinctrl {
pins_uart2: uart2 {
function = "uart2";

68
arch/mips/boot/dts/ingenic/cu1830-neo.dts
View File

@ -3,7 +3,7 @@
#include "x1830.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/clock/ingenic,sysost.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@ -31,6 +31,42 @@
};
};
ssi0: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;
mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
status = "okay";
spi-max-frequency = <50000000>;
sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */
spi-max-frequency = <4000000>;
clocks = <&exclk_sc16is752>;
interrupt-parent = <&gpb>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@ -43,13 +79,19 @@
clock-frequency = <24000000>;
};
&tcu {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
assigned-clock-rates = <1500000>, <1500000>;
&cgu {
/*
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks = <&cgu X1830_CLK_RTC>;
assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
};
/* Use channel #0 for the system timer channel #2 for the clocksource */
ingenic,pwm-channels-mask = <0xfa>;
&ost {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
&uart1 {
@ -73,6 +115,10 @@
};
};
&dtrng {
status = "okay";
};
&msc0 {
status = "okay";
@ -135,6 +181,14 @@
};
};
&otg_phy {
status = "okay";
};
&otg {
status = "okay";
};
&pinctrl {
pins_uart1: uart1 {
function = "uart1";

2
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@ -295,7 +295,7 @@
clocks = <&cgu JZ4740_CLK_DMA>;
};
uhc: uhc@13030000 {
uhc: usb@13030000 {
compatible = "ingenic,jz4740-ohci", "generic-ohci";
reg = <0x13030000 0x1000>;

2
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@ -430,7 +430,7 @@
interrupts = <23>;
};
uhc: uhc@13430000 {
uhc: usb@13430000 {
compatible = "generic-ohci";
reg = <0x13430000 0x1000>;

45
arch/mips/boot/dts/ingenic/jz4780.dtsi
View File

@ -61,13 +61,34 @@
};
cgu: jz4780-cgu@10000000 {
compatible = "ingenic,jz4780-cgu";
compatible = "ingenic,jz4780-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&ext>, <&rtc>;
clock-names = "ext", "rtc";
#clock-cells = <1>;
otg_phy: usb-phy@3c {
compatible = "ingenic,jz4780-phy";
reg = <0x3c 0x10>;
clocks = <&cgu JZ4780_CLK_OTG1>;
#phy-cells = <0>;
status = "disabled";
};
rng: rng@d8 {
compatible = "ingenic,jz4780-rng";
reg = <0xd8 0x8>;
status = "disabled";
};
};
tcu: timer@10002000 {
@ -494,4 +515,24 @@
status = "disabled";
};
otg: usb@13500000 {
compatible = "ingenic,jz4780-otg", "snps,dwc2";
reg = <0x13500000 0x40000>;
interrupt-parent = <&intc>;
interrupts = <21>;
clocks = <&cgu JZ4780_CLK_UHC>;
clock-names = "otg";
phys = <&otg_phy>;
phy-names = "usb2-phy";
g-rx-fifo-size = <768>;
g-np-tx-fifo-size = <256>;
g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
status = "disabled";
};
};

56
arch/mips/boot/dts/ingenic/x1000.dtsi
View File

@ -52,13 +52,47 @@
};
cgu: x1000-cgu@10000000 {
compatible = "ingenic,x1000-cgu";
compatible = "ingenic,x1000-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&exclk>, <&rtclk>;
clock-names = "ext", "rtc";
otg_phy: usb-phy@3c {
compatible = "ingenic,x1000-phy";
reg = <0x3c 0x10>;
clocks = <&cgu X1000_CLK_OTGPHY>;
#phy-cells = <0>;
status = "disabled";
};
rng: rng@d8 {
compatible = "ingenic,x1000-rng";
reg = <0xd8 0x8>;
status = "disabled";
};
};
ost: timer@12000000 {
compatible = "ingenic,x1000-ost";
reg = <0x12000000 0x3c>;
#clock-cells = <1>;
clocks = <&cgu X1000_CLK_OST>;
clock-names = "ost";
interrupt-parent = <&cpuintc>;
interrupts = <3>;
};
tcu: timer@10002000 {
@ -323,4 +357,24 @@
status = "disabled";
};
};
otg: usb@13500000 {
compatible = "ingenic,x1000-otg", "snps,dwc2";
reg = <0x13500000 0x40000>;
interrupt-parent = <&intc>;
interrupts = <21>;
clocks = <&cgu X1000_CLK_OTG>;
clock-names = "otg";
phys = <&otg_phy>;
phy-names = "usb2-phy";
g-rx-fifo-size = <768>;
g-np-tx-fifo-size = <256>;
g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
status = "disabled";
};
};

58
arch/mips/boot/dts/ingenic/x1830.dtsi
View File

@ -52,13 +52,40 @@
};
cgu: x1830-cgu@10000000 {
compatible = "ingenic,x1830-cgu";
compatible = "ingenic,x1830-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&exclk>, <&rtclk>;
clock-names = "ext", "rtc";
otg_phy: usb-phy@3c {
compatible = "ingenic,x1830-phy";
reg = <0x3c 0x10>;
clocks = <&cgu X1830_CLK_OTGPHY>;
#phy-cells = <0>;
status = "disabled";
};
};
ost: timer@12000000 {
compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
reg = <0x12000000 0x3c>;
#clock-cells = <1>;
clocks = <&cgu X1830_CLK_OST>;
clock-names = "ost";
interrupt-parent = <&cpuintc>;
interrupts = <4>;
};
tcu: timer@10002000 {
@ -236,6 +263,15 @@
status = "disabled";
};
dtrng: trng@10072000 {
compatible = "ingenic,x1830-dtrng";
reg = <0x10072000 0xc>;
clocks = <&cgu X1830_CLK_DTRNG>;
status = "disabled";
};
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400
@ -311,4 +347,24 @@
status = "disabled";
};
};
otg: usb@13500000 {
compatible = "ingenic,x1830-otg", "snps,dwc2";
reg = <0x13500000 0x40000>;
interrupt-parent = <&intc>;
interrupts = <21>;
clocks = <&cgu X1830_CLK_OTG>;
clock-names = "otg";
phys = <&otg_phy>;
phy-names = "usb2-phy";
g-rx-fifo-size = <768>;
g-np-tx-fifo-size = <256>;
g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
status = "disabled";
};
};

11
arch/mips/boot/dts/mscc/Makefile
View File

@ -1,4 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb
dtb-$(CONFIG_SOC_VCOREIII) += \
jaguar2_pcb110.dtb \
jaguar2_pcb111.dtb \
jaguar2_pcb118.dtb \
luton_pcb091.dtb \
ocelot_pcb120.dtb \
ocelot_pcb123.dtb \
serval_pcb105.dtb \
serval_pcb106.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

167
arch/mips/boot/dts/mscc/jaguar2.dtsi Normal file
View File

@ -0,0 +1,167 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,jr2";
aliases {
serial0 = &uart0;
serial1 = &uart2;
gpio0 = &gpio;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb: ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
intc: interrupt-controller@70000070 {
compatible = "mscc,jaguar2-icpu-intr";
reg = <0x70000070 0x94>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@70100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@70100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
gpio: pinctrl@71010038 {
compatible = "mscc,jaguar2-pinctrl";
reg = <0x71010038 0x90>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 64>;
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_24", "GPIO_25";
function = "uart2";
};
cs1_pins: cs1-pins {
pins = "GPIO_16";
function = "si";
};
cs2_pins: cs2-pins {
pins = "GPIO_17";
function = "si";
};
cs3_pins: cs3-pins {
pins = "GPIO_18";
function = "si";
};
i2c_pins: i2c-pins {
pins = "GPIO_14", "GPIO_15";
function = "twi";
};
i2c2_pins: i2c2-pins {
pins = "GPIO_28", "GPIO_29";
function = "twi2";
};
};
i2c0: i2c@70100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x70100400 0x100>, <0x700001b8 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
i2c2: i2c@70100c00 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
reg = <0x70100c00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
};
};

25
arch/mips/boot/dts/mscc/jaguar2_common.dtsi Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
#include "jaguar2.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};

267
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts Normal file
View File

@ -0,0 +1,267 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
compatible = "mscc,jr2-pcb110", "mscc,jr2";
aliases {
i2c0 = &i2c0;
i2c108 = &i2c108;
i2c109 = &i2c109;
i2c110 = &i2c110;
i2c111 = &i2c111;
i2c112 = &i2c112;
i2c113 = &i2c113;
i2c114 = &i2c114;
i2c115 = &i2c115;
i2c116 = &i2c116;
i2c117 = &i2c117;
i2c118 = &i2c118;
i2c119 = &i2c119;
i2c120 = &i2c120;
i2c121 = &i2c121;
i2c122 = &i2c122;
i2c123 = &i2c123;
i2c124 = &i2c124;
i2c125 = &i2c125;
i2c126 = &i2c126;
i2c127 = &i2c127;
i2c128 = &i2c128;
i2c129 = &i2c129;
i2c130 = &i2c130;
i2c131 = &i2c131;
i2c149 = &i2c149;
i2c150 = &i2c150;
i2c151 = &i2c151;
i2c152 = &i2c152;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c149", "i2c150", "i2c151", "i2c152", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_pins_i>;
i2c149: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c150: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c152: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
i2c0_emux: i2c0-emux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
&gpio 52 GPIO_ACTIVE_HIGH
&gpio 53 GPIO_ACTIVE_HIGH
&gpio 58 GPIO_ACTIVE_HIGH
&gpio 59 GPIO_ACTIVE_HIGH>;
idle-state = <0x0>;
i2c108: i2c@10 {
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c109: i2c@11 {
reg = <0x11>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c110: i2c@12 {
reg = <0x12>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c111: i2c@13 {
reg = <0x13>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c112: i2c@14 {
reg = <0x14>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c113: i2c@15 {
reg = <0x15>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c114: i2c@16 {
reg = <0x16>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c115: i2c@17 {
reg = <0x17>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c116: i2c@8 {
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c117: i2c@9 {
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c118: i2c@a {
reg = <0xa>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c119: i2c@b {
reg = <0xb>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c120: i2c@c {
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c121: i2c@d {
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c122: i2c@e {
reg = <0xe>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c123: i2c@f {
reg = <0xf>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
synce_pins: synce-pins {
// GPIO 16 == SI_nCS1
pins = "GPIO_16";
function = "si";
};
synce_builtin_pins: synce-builtin-pins {
// GPIO 49 == SI_nCS13
pins = "GPIO_49";
function = "si";
};
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0 {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1 {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2 {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3 {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
&i2c0 {
pca9545@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c124: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c125: i2c@1 {
/* FMC B */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c126: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c127: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
pca9545@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c128: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c129: i2c@1 {
/* FMC B */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c130: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c131: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};

107
arch/mips/boot/dts/mscc/jaguar2_pcb111.dts Normal file
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@ -0,0 +1,107 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
/ {
model = "Jaguar2 Cu48 PCB111 Reference Board";
compatible = "mscc,jr2-pcb111", "mscc,jr2";
aliases {
i2c0 = &i2c0;
i2c149 = &i2c149;
i2c150 = &i2c150;
i2c151 = &i2c151;
i2c152 = &i2c152;
i2c203 = &i2c203;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
pinctrl-5 = <&i2cmux_pins_i>;
i2c149: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c150: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c152: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c203: i2c@4 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
synce_builtin_pins: synce-builtin-pins {
// GPIO 49 == SI_nCS13
pins = "GPIO_49";
function = "si";
};
cpld_pins: cpld-pins {
// GPIO 50 == SI_nCS14
pins = "GPIO_50";
function = "si";
};
cpld_fifo_pins: synce-builtin-pins {
// GPIO 51 == SI_nCS15
pins = "GPIO_51";
function = "si";
};
};
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_17", "GPIO_18";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0 {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1 {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2 {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3 {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};

57
arch/mips/boot/dts/mscc/jaguar2_pcb118.dts Normal file
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@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
/ {
model = "Jaguar2/Aquantia PCB118 Reference Board";
compatible = "mscc,jr2-pcb118", "mscc,jr2";
aliases {
i2c150 = &i2c150;
i2c151 = &i2c151;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c150", "i2c151", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_pins_i>;
i2c150: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_17", "GPIO_16";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0 {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1 {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
};
};

116
arch/mips/boot/dts/mscc/luton.dtsi Normal file
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@ -0,0 +1,116 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 Microsemi Corporation */
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,luton";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416666666>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb@60000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x60000000 0x20000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@10000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x10000000 0x2c>;
};
intc: interrupt-controller@10000084 {
compatible = "mscc,luton-icpu-intr";
reg = <0x10000084 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@10100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x10100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c0: i2c@10100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x10100400 0x100>, <0x100002a4 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11>;
clocks = <&ahb_clk>;
status = "disabled";
};
gpio: pinctrl@70068 {
compatible = "mscc,luton-pinctrl";
reg = <0x70068 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 32>;
interrupt-controller;
interrupts = <13>;
#interrupt-cells = <2>;
i2c_pins: i2c-pins {
pins = "GPIO_5", "GPIO_6";
function = "twi";
};
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
};
};
};

30
arch/mips/boot/dts/mscc/luton_pcb091.dts Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/dts-v1/;
#include "luton.dtsi"
/ {
model = "Luton10 PCB091 Reference Board";
compatible = "mscc,luton-pcb091", "mscc,luton";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};

153
arch/mips/boot/dts/mscc/serval.dtsi Normal file
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@ -0,0 +1,153 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,serval";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
gpio0 = &gpio;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416666666>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb: ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
intc: interrupt-controller@70000070 {
compatible = "mscc,serval-icpu-intr";
reg = <0x70000070 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@70100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@70100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
gpio: pinctrl@71070034 {
compatible = "mscc,serval-pinctrl";
reg = <0x71070034 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
function = "sg0";
};
i2c_pins: i2c-pins {
pins = "GPIO_6", "GPIO_7";
function = "twi";
};
uart_pins: uart-pins {
pins = "GPIO_26", "GPIO_27";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_13", "GPIO_14";
function = "uart2";
};
cs1_pins: cs1-pins {
pins = "GPIO_8";
function = "si";
};
irqext0_pins: irqext0-pins {
pins = "GPIO_28";
function = "irq0";
};
irqext1_pins: irqext1-pins {
pins = "GPIO_29";
function = "irq1";
};
};
i2c0: i2c@70100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x70100400 0x100>, <0x70000190 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
};
};

127
arch/mips/boot/dts/mscc/serval_common.dtsi Normal file
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@ -0,0 +1,127 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
#include "serval.dtsi"
/ {
aliases {
serial0 = &uart0;
i2c104 = &i2c104;
i2c105 = &i2c105;
i2c106 = &i2c106;
i2c107 = &i2c107;
i2c108 = &i2c108;
i2c109 = &i2c109;
};
chosen {
stdout-path = "serial0:115200n8";
};
i2c0_imux: i2c0-imux{
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c104", "i2c105", "i2c106", "i2c107",
"i2c108", "i2c109", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_4>;
pinctrl-5 = <&i2cmux_5>;
pinctrl-6 = <&i2cmux_pins_i>;
i2c104: i2c_sfp0@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c105: i2c_sfp1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c106: i2c_sfp2@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c107: i2c_sfp3@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c108: i2c_sfp4@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c109: i2c_sfp5@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&gpio {
i2c_pins: i2c-pins {
pins = "GPIO_7"; /* No "default" scl for i2c0 */
function = "twi";
};
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0 {
pins = "GPIO_11";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1 {
pins = "GPIO_12";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2 {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3 {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
i2cmux_4: i2cmux-4 {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_5: i2cmux-5 {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};

17
arch/mips/boot/dts/mscc/serval_pcb105.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "serval_common.dtsi"
/ {
model = "Serval PCB105 Reference Board";
compatible = "mscc,serval-pcb105", "mscc,serval";
aliases {
};
};

17
arch/mips/boot/dts/mscc/serval_pcb106.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "serval_common.dtsi"
/ {
model = "Serval PCB106 Reference Board";
compatible = "mscc,serval-pcb106", "mscc,serval";
aliases {
};
};

2
arch/mips/boot/dts/mti/sead3.dts
View File

@ -56,7 +56,7 @@
interrupt-parent = <&cpu_intc>;
};
ehci@1b200000 {
usb@1b200000 {
compatible = "generic-ehci";
reg = <0x1b200000 0x1000>;

2
arch/mips/boot/dts/ralink/mt7628a.dtsi
View File

@ -275,7 +275,7 @@
reset-names = "host", "device";
};
ehci@101c0000 {
usb@101c0000 {
compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;

15
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -1505,10 +1505,20 @@ static int __init octeon_irq_init_ciu(
goto err;
}
r = irq_alloc_desc_at(OCTEON_IRQ_MBOX0, -1);
if (r < 0) {
pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_MBOX0");
goto err;
}
r = octeon_irq_set_ciu_mapping(
OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
if (r)
goto err;
r = irq_alloc_desc_at(OCTEON_IRQ_MBOX1, -1);
if (r < 0) {
pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_MBOX1");
goto err;
}
r = octeon_irq_set_ciu_mapping(
OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
if (r)
@ -1546,6 +1556,11 @@ static int __init octeon_irq_init_ciu(
if (r)
goto err;
r = irq_alloc_descs(OCTEON_IRQ_WDOG0, OCTEON_IRQ_WDOG0, 16, -1);
if (r < 0) {
pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_WDOGx");
goto err;
}
/* CIU_1 */
for (i = 0; i < 16; i++) {
r = octeon_irq_set_ciu_mapping(

9
arch/mips/cavium-octeon/setup.c
View File

@ -973,8 +973,6 @@ void __init plat_mem_setup(void)
uint64_t crashk_end;
#ifndef CONFIG_CRASH_DUMP
int64_t memory;
uint64_t kernel_start;
uint64_t kernel_size;
#endif
total = 0;
@ -1078,13 +1076,6 @@ void __init plat_mem_setup(void)
}
}
cvmx_bootmem_unlock();
/* Add the memory region for the kernel. */
kernel_start = (unsigned long) _text;
kernel_size = _end - _text;
/* Adjust for physical offset. */
kernel_start &= ~0xffffffff80000000ULL;
memblock_add(kernel_start, kernel_size);
#endif /* CONFIG_CRASH_DUMP */
#ifdef CONFIG_CAVIUM_RESERVE32

3
arch/mips/cavium-octeon/smp.c
View File

@ -290,9 +290,6 @@ static int octeon_cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
if (cpu == 0)
return -EBUSY;
if (!octeon_bootloader_entry_addr)
return -ENOTSUPP;

15
arch/mips/configs/ci20_defconfig
View File

@ -49,6 +49,8 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4780=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
@ -77,7 +79,6 @@ CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
@ -99,7 +100,12 @@ CONFIG_IR_GPIO_TX=m
CONFIG_MEDIA_SUPPORT=m
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC2=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
@ -131,8 +137,13 @@ CONFIG_MEMORY=y
CONFIG_JZ4780_NEMC=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=m
CONFIG_JZ4780_EFUSE=y
CONFIG_JZ4770_PHY=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y

28
arch/mips/configs/cu1000-neo_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
CONFIG_MODULES=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
@ -32,15 +33,17 @@ CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_CFG80211=y
CONFIG_CFG80211=m
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_SMSC_PHY=y
CONFIG_BRCMFMAC=y
CONFIG_BRCMFMAC=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
@ -52,16 +55,25 @@ CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_SERIAL_SC16IS7XX=y
# CONFIG_SERIAL_SC16IS7XX_I2C is not set
CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC2=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
@ -72,16 +84,22 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_INGENIC_TIMER is not set
CONFIG_INGENIC_SYSOST=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_JZ4770_PHY=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_ASCII=y

32
arch/mips/configs/cu1830-neo_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
CONFIG_MODULES=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
@ -32,18 +33,20 @@ CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_CFG80211=y
CONFIG_CFG80211=m
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_BLK_DEV_MD=m
CONFIG_BLK_DEV_DM=m
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_ICPLUS_PHY=y
CONFIG_BRCMFMAC=y
CONFIG_BRCMFMAC=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
@ -55,16 +58,25 @@ CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_SERIAL_SC16IS7XX=y
# CONFIG_SERIAL_SC16IS7XX_I2C is not set
CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC2=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
@ -75,16 +87,22 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_INGENIC_TIMER is not set
CONFIG_INGENIC_SYSOST=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_JZ4770_PHY=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_ASCII=y

1
arch/mips/configs/gcw0_defconfig
View File

@ -73,7 +73,6 @@ CONFIG_DRM_PANEL_NOVATEK_NT39016=y
CONFIG_DRM_INGENIC=y
CONFIG_DRM_ETNAVIV=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y

1
arch/mips/configs/gpr_defconfig
View File

@ -249,7 +249,6 @@ CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_VGA_ARB is not set
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB_HID=m
CONFIG_USB_HIDDEV=y

1
arch/mips/configs/lemote2f_defconfig
View File

@ -145,7 +145,6 @@ CONFIG_FB_SIS_300=y
CONFIG_FB_SIS_315=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y

1
arch/mips/configs/loongson3_defconfig
View File

@ -286,7 +286,6 @@ CONFIG_DRM_VIRTIO_GPU=y
CONFIG_FB_RADEON=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=m
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y

1
arch/mips/configs/mtx1_defconfig
View File

@ -448,7 +448,6 @@ CONFIG_WDT_MTX1=y
# CONFIG_VGA_ARB is not set
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=m
CONFIG_SND=m

1
arch/mips/configs/rs90_defconfig
View File

@ -97,7 +97,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=300
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_INGENIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y

37
arch/mips/generic/Kconfig
View File

@ -31,17 +31,22 @@ comment "MSCC Ocelot doesn't work with SEAD3 enabled"
depends on LEGACY_BOARD_SEAD3
config LEGACY_BOARD_OCELOT
bool "Support MSCC Ocelot boards"
bool "Legacy support for Ocelot based boards"
depends on LEGACY_BOARD_SEAD3=n
select LEGACY_BOARDS
select MSCC_OCELOT
select SOC_VCOREIII
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
config MSCC_OCELOT
config SOC_VCOREIII
bool
select GPIOLIB
select MSCC_OCELOT_IRQ
select MSCC_OCELOT #will be removed when driver no more use it
#Will be removed when the driver using it will be converted to SOC_VCOREIII
config MSCC_OCELOT
bool
comment "FIT/UHI Boards"
@ -67,12 +72,36 @@ config FIT_IMAGE_FDT_XILFPGA
config FIT_IMAGE_FDT_OCELOT
bool "Include FDT for Microsemi Ocelot development platforms"
select MSCC_OCELOT
select SOC_VCOREIII
help
Enable this to include the FDT for the Ocelot development platforms
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config FIT_IMAGE_FDT_LUTON
bool "Include FDT for Microsemi Luton development platforms"
select SOC_VCOREIII
help
Enable this to include the FDT for the Luton development platforms
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config FIT_IMAGE_FDT_JAGUAR2
bool "Include FDT for Microsemi Jaguar2 development platforms"
select SOC_VCOREIII
help
Enable this to include the FDT for the Jaguar2 development platforms
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config FIT_IMAGE_FDT_SERVAL
bool "Include FDT for Microsemi Serval development platforms"
select SOC_VCOREIII
help
Enable this to include the FDT for the Serval development platforms
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config BOARD_INGENIC
bool "Support boards based on Ingenic SoCs"
select MACH_INGENIC_GENERIC

3
arch/mips/generic/Platform
View File

@ -20,4 +20,7 @@ its-y := vmlinux.its.S
its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S

40
arch/mips/generic/board-jaguar2.its.S Normal file
View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/ {
images {
fdt@jaguar2_pcb110 {
description = "MSCC Jaguar2 PCB110 Device Tree";
data = /incbin/("boot/dts/mscc/jaguar2_pcb110.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
fdt@jaguar2_pcb111 {
description = "MSCC Jaguar2 PCB111 Device Tree";
data = /incbin/("boot/dts/mscc/jaguar2_pcb111.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
pcb110 {
description = "Jaguar2 Linux kernel";
kernel = "kernel@0";
fdt = "fdt@jaguar2_pcb110";
ramdisk = "ramdisk";
};
pcb111 {
description = "Jaguar2 Linux kernel";
kernel = "kernel@0";
fdt = "fdt@jaguar2_pcb111";
ramdisk = "ramdisk";
};
};
};

23
arch/mips/generic/board-luton.its.S Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/ {
images {
fdt@luton_pcb091 {
description = "MSCC Luton PCB091 Device Tree";
data = /incbin/("boot/dts/mscc/luton_pcb091.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
pcb091 {
description = "Luton Linux kernel";
kernel = "kernel@0";
fdt = "fdt@luton_pcb091";
};
};
};

24
arch/mips/generic/board-serval.its.S Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/ {
images {
fdt@serval_pcb105 {
description = "MSCC Serval PCB105 Device Tree";
data = /incbin/("boot/dts/mscc/serval_pcb105.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
pcb105 {
description = "Serval Linux kernel";
kernel = "kernel@0";
fdt = "fdt@serval_pcb105";
ramdisk = "ramdisk";
};
};
};

9
arch/mips/include/asm/compiler.h
View File

@ -43,14 +43,7 @@
#undef barrier_before_unreachable
#define barrier_before_unreachable() asm volatile(".insn")
#if !defined(CONFIG_CC_IS_GCC) || \
(__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
# define GCC_OFF_SMALL_ASM() "ZC"
#elif defined(CONFIG_CPU_MICROMIPS)
# error "microMIPS compilation unsupported with GCC older than 4.9"
#else
# define GCC_OFF_SMALL_ASM() "R"
#endif
#define GCC_OFF_SMALL_ASM() "ZC"
#ifdef CONFIG_CPU_MIPSR6
#define MIPS_ISA_LEVEL "mips64r6"

2
arch/mips/include/asm/cpu-features.h
View File

@ -115,8 +115,6 @@
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
#endif

4
arch/mips/include/asm/mach-loongson64/boot_param.h
View File

@ -228,6 +228,10 @@ struct loongson_system_configuration {
extern struct efi_memory_map_loongson *loongson_memmap;
extern struct loongson_system_configuration loongson_sysconf;
extern struct board_devices *eboard;
extern struct interface_info *einter;
extern struct loongson_special_attribute *especial;
extern u32 node_id_offset;
extern void ls7a_early_config(void);
extern void rs780e_early_config(void);

8
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
View File

@ -19,10 +19,6 @@
.macro kernel_entry_setup
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
@ -54,10 +50,6 @@
.macro smp_slave_setup
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)

10
arch/mips/include/asm/mach-loongson64/loongson_regs.h
View File

@ -227,6 +227,16 @@ static inline void csr_writeq(u64 val, u32 reg)
#define CSR_IPI_SEND_CPU_SHIFT 16
#define CSR_IPI_SEND_BLOCK BIT(31)
#define LOONGSON_CSR_MAIL_BUF0 0x1020
#define LOONGSON_CSR_MAIL_SEND 0x1048
#define CSR_MAIL_SEND_BLOCK BIT_ULL(31)
#define CSR_MAIL_SEND_BOX_LOW(box) (box << 1)
#define CSR_MAIL_SEND_BOX_HIGH(box) ((box << 1) + 1)
#define CSR_MAIL_SEND_BOX_SHIFT 2
#define CSR_MAIL_SEND_CPU_SHIFT 16
#define CSR_MAIL_SEND_BUF_SHIFT 32
#define CSR_MAIL_SEND_H32_MASK 0xFFFFFFFF00000000ULL
static inline u64 drdtime(void)
{
int rID = 0;

10
arch/mips/include/asm/pgtable.h
View File

@ -25,14 +25,8 @@
struct mm_struct;
struct vm_area_struct;
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \
_page_cachable_default)
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
_page_cachable_default)
#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \
_page_cachable_default)
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | \
_page_cachable_default)
#define PAGE_SHARED vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED)
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
_PAGE_GLOBAL | _page_cachable_default)
#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \

1
arch/mips/include/asm/types.h
View File

@ -12,6 +12,5 @@
#define _ASM_TYPES_H
#include <asm-generic/int-ll64.h>
#include <uapi/asm/types.h>
#endif /* _ASM_TYPES_H */

1
arch/mips/kernel/mips-cm.c
View File

@ -266,6 +266,7 @@ int mips_cm_probe(void)
if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
(unsigned long)addr);
iounmap(mips_gcr_base);
mips_gcr_base = NULL;
return -ENODEV;
}

13
arch/mips/kernel/relocate.c
View File

@ -64,7 +64,7 @@ static void __init sync_icache(void *kbase, unsigned long kernel_length)
: "r" (kbase));
kbase += step;
} while (kbase < kend);
} while (step && kbase < kend);
/* Completion barrier */
__sync();
@ -95,7 +95,7 @@ static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset)
/* Original target address */
target_addr <<= 2;
target_addr += (unsigned long)loc_orig & ~0x03ffffff;
target_addr += (unsigned long)loc_orig & 0xf0000000;
/* Get the new target address */
target_addr += offset;
@ -105,7 +105,7 @@ static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset)
return -ENOEXEC;
}
target_addr -= (unsigned long)loc_new & ~0x03ffffff;
target_addr -= (unsigned long)loc_new & 0xf0000000;
target_addr >>= 2;
*loc_new = (*loc_new & ~0x03ffffff) | (target_addr & 0x03ffffff);
@ -294,6 +294,13 @@ static inline int __init relocation_addr_valid(void *loc_new)
return 1;
}
#if defined(CONFIG_USE_OF)
void __weak *plat_get_fdt(void)
{
return NULL;
}
#endif
void *__init relocate_kernel(void)
{
void *loc_new;

8
arch/mips/kernel/setup.c
View File

@ -498,8 +498,8 @@ static void __init request_crashkernel(struct resource *res)
static void __init check_kernel_sections_mem(void)
{
phys_addr_t start = PFN_PHYS(PFN_DOWN(__pa_symbol(&_text)));
phys_addr_t size = PFN_PHYS(PFN_UP(__pa_symbol(&_end))) - start;
phys_addr_t start = __pa_symbol(&_text);
phys_addr_t size = __pa_symbol(&_end) - start;
if (!memblock_is_region_memory(start, size)) {
pr_info("Kernel sections are not in the memory maps\n");
@ -688,8 +688,6 @@ static void __init arch_mem_init(char **cmdline_p)
fdt_init_reserved_mem();
memblock_dump_all();
early_memtest(PFN_PHYS(ARCH_PFN_OFFSET), PFN_PHYS(max_low_pfn));
}
@ -787,6 +785,8 @@ void __init setup_arch(char **cmdline_p)
cpu_cache_init();
paging_init();
memblock_dump_all();
}
unsigned long kernelsp[NR_CPUS];

3
arch/mips/kernel/smp-bmips.c
View File

@ -362,9 +362,6 @@ static int bmips_cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
if (cpu == 0)
return -EBUSY;
pr_info("SMP: CPU%d is offline\n", cpu);
set_cpu_online(cpu, false);

2
arch/mips/kernel/smp-cps.c
View File

@ -12,6 +12,7 @@
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <asm/bcache.h>
#include <asm/mips-cps.h>
@ -461,6 +462,7 @@ static int cps_cpu_disable(void)
smp_mb__after_atomic();
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
irq_migrate_all_off_this_cpu();
return 0;
}

4
arch/mips/kernel/vdso.c
View File

@ -161,7 +161,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
gic_pfn = virt_to_phys(mips_gic_base + MIPS_GIC_USER_OFS) >> PAGE_SHIFT;
ret = io_remap_pfn_range(vma, base, gic_pfn, gic_size,
pgprot_noncached(PAGE_READONLY));
pgprot_noncached(vma->vm_page_prot));
if (ret)
goto out;
}
@ -169,7 +169,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
/* Map data page. */
ret = remap_pfn_range(vma, data_addr,
virt_to_phys(vdso_data) >> PAGE_SHIFT,
PAGE_SIZE, PAGE_READONLY);
PAGE_SIZE, vma->vm_page_prot);
if (ret)
goto out;

4
arch/mips/kvm/mmu.c
View File

@ -1074,6 +1074,7 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
{
kvm_pfn_t pfn;
pte_t *ptep;
pgprot_t prot;
ptep = kvm_trap_emul_pte_for_gva(vcpu, badvaddr);
if (!ptep) {
@ -1083,7 +1084,8 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
pfn = PFN_DOWN(virt_to_phys(vcpu->arch.kseg0_commpage));
/* Also set valid and dirty, so refill handler doesn't have to */
*ptep = pte_mkyoung(pte_mkdirty(pfn_pte(pfn, PAGE_SHARED)));
prot = vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED);
*ptep = pte_mkyoung(pte_mkdirty(pfn_pte(pfn, prot)));
/* Invalidate this entry in the TLB, guest kernel ASID only */
kvm_mips_host_tlb_inv(vcpu, badvaddr, false, true);

4
arch/mips/lib/uncached.c
View File

@ -37,10 +37,12 @@
*/
unsigned long run_uncached(void *func)
{
register long sp __asm__("$sp");
register long ret __asm__("$2");
long lfunc = (long)func, ufunc;
long usp;
long sp;
__asm__("move %0, $sp" : "=r" (sp));
if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
usp = CKSEG1ADDR(sp);

1
arch/mips/loongson64/Makefile
View File

@ -11,3 +11,4 @@ obj-$(CONFIG_RS780_HPET) += hpet.o
obj-$(CONFIG_SUSPEND) += pm.o
obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o
obj-$(CONFIG_SYSFS) += boardinfo.o

48
arch/mips/loongson64/boardinfo.c Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/kobject.h>
#include <boot_param.h>
static ssize_t boardinfo_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
char board_manufacturer[64] = {0};
char *tmp_board_manufacturer = board_manufacturer;
char bios_vendor[64] = {0};
char *tmp_bios_vendor = bios_vendor;
strcpy(board_manufacturer, eboard->name);
strcpy(bios_vendor, einter->description);
return sprintf(buf,
"Board Info\n"
"Manufacturer\t\t: %s\n"
"Board Name\t\t: %s\n"
"Family\t\t\t: LOONGSON3\n\n"
"BIOS Info\n"
"Vendor\t\t\t: %s\n"
"Version\t\t\t: %s\n"
"ROM Size\t\t: %d KB\n"
"Release Date\t\t: %s\n",
strsep(&tmp_board_manufacturer, "-"),
eboard->name,
strsep(&tmp_bios_vendor, "-"),
einter->description,
einter->size,
especial->special_name);
}
static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,
boardinfo_show, NULL);
static int __init boardinfo_init(void)
{
struct kobject *lefi_kobj;
lefi_kobj = kobject_create_and_add("lefi", firmware_kobj);
if (!lefi_kobj) {
pr_err("lefi: Firmware registration failed.\n");
return -ENOMEM;
}
return sysfs_create_file(lefi_kobj, &boardinfo_attr.attr);
}
late_initcall(boardinfo_init);

10
arch/mips/loongson64/env.c
View File

@ -28,6 +28,10 @@ EXPORT_SYMBOL(cpu_clock_freq);
struct efi_memory_map_loongson *loongson_memmap;
struct loongson_system_configuration loongson_sysconf;
struct board_devices *eboard;
struct interface_info *einter;
struct loongson_special_attribute *especial;
u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
u64 loongson_chiptemp[MAX_PACKAGES];
u64 loongson_freqctrl[MAX_PACKAGES];
@ -57,6 +61,12 @@ void __init prom_init_env(void)
((u64)loongson_p + loongson_p->system_offset);
ecpu = (struct efi_cpuinfo_loongson *)
((u64)loongson_p + loongson_p->cpu_offset);
eboard = (struct board_devices *)
((u64)loongson_p + loongson_p->boarddev_table_offset);
einter = (struct interface_info *)
((u64)loongson_p + loongson_p->interface_offset);
especial = (struct loongson_special_attribute *)
((u64)loongson_p + loongson_p->special_offset);
eirq_source = (struct irq_source_routing_table *)
((u64)loongson_p + loongson_p->irq_offset);
loongson_memmap = (struct efi_memory_map_loongson *)

27
arch/mips/loongson64/numa.c
View File

@ -35,23 +35,6 @@ EXPORT_SYMBOL(__node_data);
cpumask_t __node_cpumask[MAX_NUMNODES];
EXPORT_SYMBOL(__node_cpumask);
static void enable_lpa(void)
{
unsigned long value;
value = __read_32bit_c0_register($16, 3);
value |= 0x00000080;
__write_32bit_c0_register($16, 3, value);
value = __read_32bit_c0_register($16, 3);
pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
value = __read_32bit_c0_register($5, 1);
value |= 0x20000000;
__write_32bit_c0_register($5, 1, value);
value = __read_32bit_c0_register($5, 1);
pr_info("CP0_PageGrain: CP0 5.1 (0x%lx)\n", value);
}
static void cpu_node_probe(void)
{
int i;
@ -168,6 +151,9 @@ static void __init node_mem_init(unsigned int node)
NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
if (node == 0) {
/* kernel start address */
unsigned long kernel_start_pfn = PFN_DOWN(__pa_symbol(&_text));
/* kernel end address */
unsigned long kernel_end_pfn = PFN_UP(__pa_symbol(&_end));
@ -175,8 +161,8 @@ static void __init node_mem_init(unsigned int node)
max_low_pfn = end_pfn;
/* Reserve the kernel text/data/bss */
memblock_reserve(start_pfn << PAGE_SHIFT,
((kernel_end_pfn - start_pfn) << PAGE_SHIFT));
memblock_reserve(kernel_start_pfn << PAGE_SHIFT,
((kernel_end_pfn - kernel_start_pfn) << PAGE_SHIFT));
/* Reserve 0xfe000000~0xffffffff for RS780E integrated GPU */
if (node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT))
@ -243,7 +229,8 @@ EXPORT_SYMBOL(pcibus_to_node);
void __init prom_init_numa_memory(void)
{
enable_lpa();
pr_info("CP0_Config3: CP0 16.3 (0x%x)\n", read_c0_config3());
pr_info("CP0_PageGrain: CP0 5.1 (0x%x)\n", read_c0_pagegrain());
prom_meminit();
}
EXPORT_SYMBOL(prom_init_numa_memory);

126
arch/mips/loongson64/smp.c
View File

@ -53,6 +53,29 @@ static uint32_t core0_c0count[NR_CPUS];
u32 (*ipi_read_clear)(int cpu);
void (*ipi_write_action)(int cpu, u32 action);
void (*ipi_write_enable)(int cpu);
void (*ipi_clear_buf)(int cpu);
void (*ipi_write_buf)(int cpu, struct task_struct *idle);
/* send mail via Mail_Send register for 3A4000+ CPU */
static void csr_mail_send(uint64_t data, int cpu, int mailbox)
{
uint64_t val;
/* send high 32 bits */
val = CSR_MAIL_SEND_BLOCK;
val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
val |= (data & CSR_MAIL_SEND_H32_MASK);
csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
/* send low 32 bits */
val = CSR_MAIL_SEND_BLOCK;
val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
val |= (data << CSR_MAIL_SEND_BUF_SHIFT);
csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
};
static u32 csr_ipi_read_clear(int cpu)
{
@ -79,6 +102,35 @@ static void csr_ipi_write_action(int cpu, u32 action)
}
}
static void csr_ipi_write_enable(int cpu)
{
csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN);
}
static void csr_ipi_clear_buf(int cpu)
{
csr_writeq(0, LOONGSON_CSR_MAIL_BUF0);
}
static void csr_ipi_write_buf(int cpu, struct task_struct *idle)
{
unsigned long startargs[4];
/* startargs[] are initial PC, SP and GP for secondary CPU */
startargs[0] = (unsigned long)&smp_bootstrap;
startargs[1] = (unsigned long)__KSTK_TOS(idle);
startargs[2] = (unsigned long)task_thread_info(idle);
startargs[3] = 0;
pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
cpu, startargs[0], startargs[1], startargs[2]);
csr_mail_send(startargs[3], cpu_logical_map(cpu), 3);
csr_mail_send(startargs[2], cpu_logical_map(cpu), 2);
csr_mail_send(startargs[1], cpu_logical_map(cpu), 1);
csr_mail_send(startargs[0], cpu_logical_map(cpu), 0);
}
static u32 legacy_ipi_read_clear(int cpu)
{
u32 action;
@ -96,14 +148,53 @@ static void legacy_ipi_write_action(int cpu, u32 action)
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
}
static void legacy_ipi_write_enable(int cpu)
{
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
}
static void legacy_ipi_clear_buf(int cpu)
{
loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
}
static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
{
unsigned long startargs[4];
/* startargs[] are initial PC, SP and GP for secondary CPU */
startargs[0] = (unsigned long)&smp_bootstrap;
startargs[1] = (unsigned long)__KSTK_TOS(idle);
startargs[2] = (unsigned long)task_thread_info(idle);
startargs[3] = 0;
pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
cpu, startargs[0], startargs[1], startargs[2]);
loongson3_ipi_write64(startargs[3],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
loongson3_ipi_write64(startargs[2],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
loongson3_ipi_write64(startargs[1],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
loongson3_ipi_write64(startargs[0],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
}
static void csr_ipi_probe(void)
{
if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) {
ipi_read_clear = csr_ipi_read_clear;
ipi_write_action = csr_ipi_write_action;
ipi_write_enable = csr_ipi_write_enable;
ipi_clear_buf = csr_ipi_clear_buf;
ipi_write_buf = csr_ipi_write_buf;
} else {
ipi_read_clear = legacy_ipi_read_clear;
ipi_write_action = legacy_ipi_write_action;
ipi_write_enable = legacy_ipi_write_enable;
ipi_clear_buf = legacy_ipi_clear_buf;
ipi_write_buf = legacy_ipi_write_buf;
}
}
@ -347,9 +438,7 @@ static void loongson3_init_secondary(void)
/* Set interrupt mask, but don't enable */
change_c0_status(ST0_IM, imask);
for (i = 0; i < num_possible_cpus(); i++)
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
ipi_write_enable(cpu);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
cpu_set_core(&cpu_data[cpu],
@ -381,8 +470,8 @@ static void loongson3_smp_finish(void)
write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
local_irq_enable();
loongson3_ipi_write64(0,
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
ipi_clear_buf(cpu);
pr_info("CPU#%d finished, CP0_ST=%x\n",
smp_processor_id(), read_c0_status());
}
@ -420,6 +509,8 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
ipi_write_enable(0);
cpu_set_core(&cpu_data[0],
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
@ -439,27 +530,10 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
*/
static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
{
unsigned long startargs[4];
pr_info("Booting CPU#%d...\n", cpu);
/* startargs[] are initial PC, SP and GP for secondary CPU */
startargs[0] = (unsigned long)&smp_bootstrap;
startargs[1] = (unsigned long)__KSTK_TOS(idle);
startargs[2] = (unsigned long)task_thread_info(idle);
startargs[3] = 0;
ipi_write_buf(cpu, idle);
pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
cpu, startargs[0], startargs[1], startargs[2]);
loongson3_ipi_write64(startargs[3],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
loongson3_ipi_write64(startargs[2],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
loongson3_ipi_write64(startargs[1],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
loongson3_ipi_write64(startargs[0],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
return 0;
}
@ -470,9 +544,6 @@ static int loongson3_cpu_disable(void)
unsigned long flags;
unsigned int cpu = smp_processor_id();
if (cpu == 0)
return -EBUSY;
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
@ -690,9 +761,10 @@ static void loongson3_type3_play_dead(int *state_addr)
"1: li %[count], 0x100 \n" /* wait for init loop */
"2: bnez %[count], 2b \n" /* limit mailbox access */
" addiu %[count], -1 \n"
" ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
" lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */
" beqz %[initfunc], 1b \n"
" nop \n"
" ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */
" ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
" ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
" ld $a1, 0x38(%[base]) \n"

12
arch/mips/mm/c-r4k.c
View File

@ -1609,7 +1609,7 @@ static void __init loongson2_sc_init(void)
c->options |= MIPS_CPU_INCLUSIVE_CACHES;
}
static void __init loongson3_sc_init(void)
static void loongson3_sc_init(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
unsigned int config2, lsize;
@ -1623,15 +1623,13 @@ static void __init loongson3_sc_init(void)
c->scache.sets = 64 << ((config2 >> 8) & 15);
c->scache.ways = 1 + (config2 & 15);
scache_size = c->scache.sets *
c->scache.ways *
c->scache.linesz;
/* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
scache_size *= 2;
c->scache.sets *= 2;
else
scache_size *= 4;
c->scache.sets *= 4;
scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
c->scache.waybit = 0;
c->scache.waysize = scache_size / c->scache.ways;

67
arch/mips/mm/cache.c
View File

@ -155,47 +155,32 @@ void __update_cache(unsigned long address, pte_t pte)
unsigned long _page_cachable_default;
EXPORT_SYMBOL(_page_cachable_default);
#define PM(p) __pgprot(_page_cachable_default | (p))
static inline void setup_protection_map(void)
{
if (cpu_has_rixi) {
protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[0] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[1] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[2] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[3] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[4] = PM(_PAGE_PRESENT);
protection_map[5] = PM(_PAGE_PRESENT);
protection_map[6] = PM(_PAGE_PRESENT);
protection_map[7] = PM(_PAGE_PRESENT);
protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ);
protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE);
protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE);
} else {
protection_map[0] = PAGE_NONE;
protection_map[1] = PAGE_READONLY;
protection_map[2] = PAGE_COPY;
protection_map[3] = PAGE_COPY;
protection_map[4] = PAGE_READONLY;
protection_map[5] = PAGE_READONLY;
protection_map[6] = PAGE_COPY;
protection_map[7] = PAGE_COPY;
protection_map[8] = PAGE_NONE;
protection_map[9] = PAGE_READONLY;
protection_map[10] = PAGE_SHARED;
protection_map[11] = PAGE_SHARED;
protection_map[12] = PAGE_READONLY;
protection_map[13] = PAGE_READONLY;
protection_map[14] = PAGE_SHARED;
protection_map[15] = PAGE_SHARED;
}
protection_map[8] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[9] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[10] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE |
_PAGE_NO_READ);
protection_map[11] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
protection_map[12] = PM(_PAGE_PRESENT);
protection_map[13] = PM(_PAGE_PRESENT);
protection_map[14] = PM(_PAGE_PRESENT | _PAGE_WRITE);
protection_map[15] = PM(_PAGE_PRESENT | _PAGE_WRITE);
}
#undef PM
void cpu_cache_init(void)
{
if (cpu_has_3k_cache) {
@ -203,21 +188,11 @@ void cpu_cache_init(void)
r3k_cache_init();
}
if (cpu_has_6k_cache) {
extern void __weak r6k_cache_init(void);
r6k_cache_init();
}
if (cpu_has_4k_cache) {
extern void __weak r4k_cache_init(void);
r4k_cache_init();
}
if (cpu_has_8k_cache) {
extern void __weak r8k_cache_init(void);
r8k_cache_init();
}
if (cpu_has_tx39_cache) {
extern void __weak tx39_cache_init(void);

12
arch/mips/mm/hugetlbpage.c
View File

@ -58,18 +58,6 @@ pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr,
return (pte_t *) pmd;
}
/*
* This function checks for proper alignment of input addr and len parameters.
*/
int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
{
if (len & ~HPAGE_MASK)
return -EINVAL;
if (addr & ~HPAGE_MASK)
return -EINVAL;
return 0;
}
int pmd_huge(pmd_t pmd)
{
return (pmd_val(pmd) & _PAGE_HUGE) != 0;

4
arch/mips/mm/sc-mips.c
View File

@ -146,7 +146,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
return 1;
}
static int __init mips_sc_probe_cm3(void)
static int mips_sc_probe_cm3(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
unsigned long cfg = read_gcr_l2_config();
@ -180,7 +180,7 @@ static int __init mips_sc_probe_cm3(void)
return 0;
}
static inline int __init mips_sc_probe(void)
static inline int mips_sc_probe(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
unsigned int config1, config2;

4
arch/mips/pci/pci-vr41xx.c
View File

@ -293,8 +293,10 @@ static int __init vr41xx_pciu_init(void)
master = setup->master_io;
io_map_base = ioremap(master->bus_base_address,
resource_size(res));
if (!io_map_base)
if (!io_map_base) {
iounmap(pciu_base);
return -EBUSY;
}
vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
}

4
drivers/bus/mips_cdmm.c
View File

@ -559,10 +559,8 @@ static void mips_cdmm_bus_discover(struct mips_cdmm_bus *bus)
dev_set_name(&dev->dev, "cdmm%u-%u", cpu, id);
++id;
ret = device_register(&dev->dev);
if (ret) {
if (ret)
put_device(&dev->dev);
kfree(dev);
}
}
}

7
drivers/reset/Kconfig
View File

@ -35,6 +35,13 @@ config RESET_AXS10X
help
This enables the reset controller driver for AXS10x.
config RESET_BCM6345
bool "BCM6345 Reset Controller"
depends on BMIPS_GENERIC || COMPILE_TEST
default BMIPS_GENERIC
help
This enables the reset controller driver for BCM6345 SoCs.
config RESET_BERLIN
bool "Berlin Reset Driver" if COMPILE_TEST
default ARCH_BERLIN

1
drivers/reset/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o

135
drivers/reset/reset-bcm6345.c Normal file
View File

@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* BCM6345 Reset Controller Driver
*
* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#define BCM6345_RESET_NUM 32
#define BCM6345_RESET_SLEEP_MIN_US 10000
#define BCM6345_RESET_SLEEP_MAX_US 20000
struct bcm6345_reset {
struct reset_controller_dev rcdev;
void __iomem *base;
spinlock_t lock;
};
static inline struct bcm6345_reset *
to_bcm6345_reset(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct bcm6345_reset, rcdev);
}
static int bcm6345_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev);
unsigned long flags;
uint32_t val;
spin_lock_irqsave(&bcm6345_reset->lock, flags);
val = __raw_readl(bcm6345_reset->base);
if (assert)
val &= ~BIT(id);
else
val |= BIT(id);
__raw_writel(val, bcm6345_reset->base);
spin_unlock_irqrestore(&bcm6345_reset->lock, flags);
return 0;
}
static int bcm6345_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return bcm6345_reset_update(rcdev, id, true);
}
static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return bcm6345_reset_update(rcdev, id, false);
}
static int bcm6345_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
bcm6345_reset_update(rcdev, id, true);
usleep_range(BCM6345_RESET_SLEEP_MIN_US,
BCM6345_RESET_SLEEP_MAX_US);
bcm6345_reset_update(rcdev, id, false);
/*
* Ensure component is taken out reset state by sleeping also after
* deasserting the reset. Otherwise, the component may not be ready
* for operation.
*/
usleep_range(BCM6345_RESET_SLEEP_MIN_US,
BCM6345_RESET_SLEEP_MAX_US);
return 0;
}
static int bcm6345_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev);
return !(__raw_readl(bcm6345_reset->base) & BIT(id));
}
static struct reset_control_ops bcm6345_reset_ops = {
.assert = bcm6345_reset_assert,
.deassert = bcm6345_reset_deassert,
.reset = bcm6345_reset_reset,
.status = bcm6345_reset_status,
};
static int bcm6345_reset_probe(struct platform_device *pdev)
{
struct bcm6345_reset *bcm6345_reset;
bcm6345_reset = devm_kzalloc(&pdev->dev,
sizeof(*bcm6345_reset), GFP_KERNEL);
if (!bcm6345_reset)
return -ENOMEM;
platform_set_drvdata(pdev, bcm6345_reset);
bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(bcm6345_reset->base))
return PTR_ERR(bcm6345_reset->base);
spin_lock_init(&bcm6345_reset->lock);
bcm6345_reset->rcdev.ops = &bcm6345_reset_ops;
bcm6345_reset->rcdev.owner = THIS_MODULE;
bcm6345_reset->rcdev.of_node = pdev->dev.of_node;
bcm6345_reset->rcdev.of_reset_n_cells = 1;
bcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM;
return devm_reset_controller_register(&pdev->dev,
&bcm6345_reset->rcdev);
}
static const struct of_device_id bcm6345_reset_of_match[] = {
{ .compatible = "brcm,bcm6345-reset" },
{ /* sentinel */ },
};
static struct platform_driver bcm6345_reset_driver = {
.probe = bcm6345_reset_probe,
.driver = {
.name = "bcm6345-reset",
.of_match_table = bcm6345_reset_of_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver(bcm6345_reset_driver);

20
include/dt-bindings/reset/bcm6318-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6318_H
#define __DT_BINDINGS_RESET_BCM6318_H
#define BCM6318_RST_SPI 0
#define BCM6318_RST_EPHY 1
#define BCM6318_RST_SAR 2
#define BCM6318_RST_ENETSW 3
#define BCM6318_RST_USBD 4
#define BCM6318_RST_USBH 5
#define BCM6318_RST_PCIE_CORE 6
#define BCM6318_RST_PCIE 7
#define BCM6318_RST_PCIE_EXT 8
#define BCM6318_RST_PCIE_HARD 9
#define BCM6318_RST_ADSL 10
#define BCM6318_RST_PHYMIPS 11
#define BCM6318_RST_HOSTMIPS 12
#endif /* __DT_BINDINGS_RESET_BCM6318_H */

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include/dt-bindings/reset/bcm63268-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM63268_H
#define __DT_BINDINGS_RESET_BCM63268_H
#define BCM63268_RST_SPI 0
#define BCM63268_RST_IPSEC 1
#define BCM63268_RST_EPHY 2
#define BCM63268_RST_SAR 3
#define BCM63268_RST_ENETSW 4
#define BCM63268_RST_USBS 5
#define BCM63268_RST_USBH 6
#define BCM63268_RST_PCM 7
#define BCM63268_RST_PCIE_CORE 8
#define BCM63268_RST_PCIE 9
#define BCM63268_RST_PCIE_EXT 10
#define BCM63268_RST_WLAN_SHIM 11
#define BCM63268_RST_DDR_PHY 12
#define BCM63268_RST_FAP0 13
#define BCM63268_RST_WLAN_UBUS 14
#define BCM63268_RST_DECT 15
#define BCM63268_RST_FAP1 16
#define BCM63268_RST_PCIE_HARD 17
#define BCM63268_RST_GPHY 18
#endif /* __DT_BINDINGS_RESET_BCM63268_H */

18
include/dt-bindings/reset/bcm6328-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6328_H
#define __DT_BINDINGS_RESET_BCM6328_H
#define BCM6328_RST_SPI 0
#define BCM6328_RST_EPHY 1
#define BCM6328_RST_SAR 2
#define BCM6328_RST_ENETSW 3
#define BCM6328_RST_USBS 4
#define BCM6328_RST_USBH 5
#define BCM6328_RST_PCM 6
#define BCM6328_RST_PCIE_CORE 7
#define BCM6328_RST_PCIE 8
#define BCM6328_RST_PCIE_EXT 9
#define BCM6328_RST_PCIE_HARD 10
#endif /* __DT_BINDINGS_RESET_BCM6328_H */

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include/dt-bindings/reset/bcm6358-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6358_H
#define __DT_BINDINGS_RESET_BCM6358_H
#define BCM6358_RST_SPI 0
#define BCM6358_RST_ENET 2
#define BCM6358_RST_MPI 3
#define BCM6358_RST_EPHY 6
#define BCM6358_RST_SAR 7
#define BCM6358_RST_USBH 12
#define BCM6358_RST_PCM 13
#define BCM6358_RST_ADSL 14
#endif /* __DT_BINDINGS_RESET_BCM6358_H */

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include/dt-bindings/reset/bcm6362-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6362_H
#define __DT_BINDINGS_RESET_BCM6362_H
#define BCM6362_RST_SPI 0
#define BCM6362_RST_IPSEC 1
#define BCM6362_RST_EPHY 2
#define BCM6362_RST_SAR 3
#define BCM6362_RST_ENETSW 4
#define BCM6362_RST_USBD 5
#define BCM6362_RST_USBH 6
#define BCM6362_RST_PCM 7
#define BCM6362_RST_PCIE_CORE 8
#define BCM6362_RST_PCIE 9
#define BCM6362_RST_PCIE_EXT 10
#define BCM6362_RST_WLAN_SHIM 11
#define BCM6362_RST_DDR_PHY 12
#define BCM6362_RST_FAP 13
#define BCM6362_RST_WLAN_UBUS 14
#endif /* __DT_BINDINGS_RESET_BCM6362_H */

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include/dt-bindings/reset/bcm6368-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6368_H
#define __DT_BINDINGS_RESET_BCM6368_H
#define BCM6368_RST_SPI 0
#define BCM6368_RST_MPI 3
#define BCM6368_RST_IPSEC 4
#define BCM6368_RST_EPHY 6
#define BCM6368_RST_SAR 7
#define BCM6368_RST_SWITCH 10
#define BCM6368_RST_USBD 11
#define BCM6368_RST_USBH 12
#define BCM6368_RST_PCM 13
#endif /* __DT_BINDINGS_RESET_BCM6368_H */

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include/linux/platform_data/jz4740/jz4740_nand.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 SoC NAND controller driver
*/
#ifndef __JZ4740_NAND_H__
#define __JZ4740_NAND_H__
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#define JZ_NAND_NUM_BANKS 4
struct jz_nand_platform_data {
int num_partitions;
struct mtd_partition *partitions;
unsigned char banks[JZ_NAND_NUM_BANKS];
void (*ident_callback)(struct platform_device *, struct mtd_info *,
struct mtd_partition **, int *num_partitions);
};
#endif