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[ARM] Feroceon: L1 cache range operation support
This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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2 changed files with 69 additions and 6 deletions
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@ -237,6 +237,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_flush_kern_dcache_page)
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mrs r2, cpsr
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add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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@ -253,10 +267,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
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.align 5
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ENTRY(feroceon_dma_inv_range)
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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@ -264,6 +278,22 @@ ENTRY(feroceon_dma_inv_range)
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_inv_range)
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mrs r2, cpsr
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c14, 0 @ D inv range start
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mcr p15, 5, r1, c15, c14, 1 @ D inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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@ -284,6 +314,19 @@ ENTRY(feroceon_dma_clean_range)
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_clean_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c13, 0 @ D clean range start
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mcr p15, 5, r1, c15, c13, 1 @ D clean range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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@ -302,6 +345,19 @@ ENTRY(feroceon_dma_flush_range)
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_flush_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(feroceon_cache_fns)
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.long feroceon_flush_kern_cache_all
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.long feroceon_flush_user_cache_all
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@ -313,6 +369,17 @@ ENTRY(feroceon_cache_fns)
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.long feroceon_dma_clean_range
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.long feroceon_dma_flush_range
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ENTRY(feroceon_range_cache_fns)
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.long feroceon_flush_kern_cache_all
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.long feroceon_flush_user_cache_all
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.long feroceon_flush_user_cache_range
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.long feroceon_coherent_kern_range
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.long feroceon_coherent_user_range
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.long feroceon_range_flush_kern_dcache_page
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.long feroceon_range_dma_inv_range
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.long feroceon_range_dma_clean_range
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.long feroceon_range_dma_flush_range
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.align 5
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ENTRY(cpu_feroceon_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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@ -95,11 +95,7 @@
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#endif
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#if defined(CONFIG_CPU_FEROCEON)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE feroceon
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# endif
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V6)
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