From 83856aaab45da0fd34f94aac0371ba80668c1dbc Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sat, 13 Aug 2022 17:06:00 +0100 Subject: [PATCH] staging: iio: frequency: ad9832: Fix alignment for DMA safety ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Whilst here, move the marking to cover the whole union. That has no functional affect, but makes it slightly easier to see what is going on. Signed-off-by: Jonathan Cameron Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20220813160600.1157169-1-jic23@kernel.org --- drivers/staging/iio/frequency/ad9832.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c index f43464db618a..6f9eebd6c7ee 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -112,10 +112,10 @@ struct ad9832_state { * transfer buffers to live in their own cache lines. */ union { - __be16 freq_data[4]____cacheline_aligned; + __be16 freq_data[4]; __be16 phase_data[2]; __be16 data; - }; + } __aligned(IIO_DMA_MINALIGN); }; static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)