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clk: bcm2835: Round UART input clock up
[ Upstream commitf690a4d7a8
] It was reported that RPi3[1] and RPi Zero 2W boards have issues with the Bluetooth. It turns out that when switching from initial to operation speed host and device no longer can talk each other because host uses incorrect UART baud rate. The UART driver used in this case is amba-pl011. Original fix, see below Github link[2], was inside pl011 module, but somehow it didn't look as the right place to fix. Beside that this original rounding function is not exactly perfect for all possible clock values. So I deiced to move the hack to the platform which actually need it. The UART clock is initialised to be as close to the requested frequency as possible without exceeding it. Now that there is a clock manager that returns the actual frequencies, an expected 48MHz clock is reported as 47999625. If the requested baud rate == requested clock/16, there is no headroom and the slight reduction in actual clock rate results in failure. If increasing a clock by less than 0.1% changes it from ..999.. to ..000.., round it up. [1] https://bugzilla.suse.com/show_bug.cgi?id=1188238 [2]ab3f1b3953
Cc: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Link: https://lore.kernel.org/r/20220912081306.24662-1-iivanov@suse.de Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 33 additions and 2 deletions
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@ -30,6 +30,7 @@
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/math.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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@ -502,6 +503,8 @@ struct bcm2835_clock_data {
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bool low_jitter;
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u32 tcnt_mux;
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bool round_up;
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};
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struct bcm2835_gate_data {
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@ -993,12 +996,34 @@ static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock
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return temp;
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}
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static unsigned long bcm2835_round_rate(unsigned long rate)
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{
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unsigned long scaler;
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unsigned long limit;
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limit = rate / 100000;
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scaler = 1;
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while (scaler < limit)
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scaler *= 10;
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/*
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* If increasing a clock by less than 0.1% changes it
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* from ..999.. to ..000.., round up.
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*/
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if ((rate + scaler - 1) / scaler % 1000 == 0)
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rate = roundup(rate, scaler);
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return rate;
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}
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static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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const struct bcm2835_clock_data *data = clock->data;
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unsigned long rate;
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u32 div;
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if (data->int_bits == 0 && data->frac_bits == 0)
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@ -1006,7 +1031,12 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
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div = cprman_read(cprman, data->div_reg);
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return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
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rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
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if (data->round_up)
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rate = bcm2835_round_rate(rate);
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return rate;
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}
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static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
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@ -2143,7 +2173,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.div_reg = CM_UARTDIV,
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.int_bits = 10,
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.frac_bits = 12,
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.tcnt_mux = 28),
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.tcnt_mux = 28,
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.round_up = true),
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/* TV encoder clock. Only operating frequency is 108Mhz. */
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[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
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