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clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT

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Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Eugen Hristev 2020-11-19 17:43:09 +02:00 committed by Stephen Boyd
parent 3d86ee17d4
commit 83d0028773
1 changed files with 4 additions and 2 deletions
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6
drivers/clk/at91/sama7g5.c
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@ -117,7 +117,8 @@ static const struct {
.p = "cpupll_fracck",
.l = &pll_layout_divpmc,
.t = PLL_TYPE_DIV,
.c = 1, },
.c = 1,
.eid = PMC_CPUPLL, },
},
[PLL_ID_SYS] = {
@ -131,7 +132,8 @@ static const struct {
.p = "syspll_fracck",
.l = &pll_layout_divpmc,
.t = PLL_TYPE_DIV,
.c = 1, },
.c = 1,
.eid = PMC_SYSPLL, },
},
[PLL_ID_DDR] = {