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MIPS: Octeon: Remove extern declarations.
Get rid of extern declarations in .c functions and included the necessary header file. Also remove unused UART declares. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19477/ Cc: linux-mips@linux-mips.org
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6312455a04
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840267e446
12 changed files with 30 additions and 34 deletions
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -42,9 +42,6 @@
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#include <asm/octeon/cvmx-asxx-defs.h>
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#include <asm/octeon/cvmx-dbg-defs.h>
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void __cvmx_interrupt_gmxx_enable(int interface);
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void __cvmx_interrupt_asxx_enable(int block);
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/**
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* Probe RGMII ports and determine the number present
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*
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -39,10 +39,7 @@
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-pcsx-defs.h>
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void __cvmx_interrupt_gmxx_enable(int interface);
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void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
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void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
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#include <asm/octeon/cvmx-pcsxx-defs.h>
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/**
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* Perform initialization required only once for an SGMII port.
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -25,10 +25,6 @@
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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void __cvmx_interrupt_gmxx_enable(int interface);
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void __cvmx_interrupt_spxx_int_msk_enable(int index);
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void __cvmx_interrupt_stxx_int_msk_enable(int index);
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/*
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* Functions for SPI initialization, configuration,
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* and monitoring.
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@ -41,6 +37,8 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
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#include <asm/octeon/cvmx-pip-defs.h>
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#include <asm/octeon/cvmx-pko-defs.h>
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#include <asm/octeon/cvmx-spxx-defs.h>
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#include <asm/octeon/cvmx-stxx-defs.h>
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/*
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* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -39,12 +39,9 @@
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#include <asm/octeon/cvmx-pko-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-pcsx-defs.h>
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#include <asm/octeon/cvmx-pcsxx-defs.h>
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void __cvmx_interrupt_gmxx_enable(int interface);
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void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
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void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
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int __cvmx_helper_xaui_enumerate(int interface)
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{
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union cvmx_gmxx_hg2_control gmx_hg2_control;
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@ -1154,11 +1154,7 @@ void __init prom_free_prom_memory(void)
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}
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void __init octeon_fill_mac_addresses(void);
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int octeon_prune_device_tree(void);
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extern const char __appended_dtb;
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extern const char __dtb_octeon_3xxx_begin;
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extern const char __dtb_octeon_68xx_begin;
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void __init device_tree_init(void)
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{
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const void *fdt;
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -55,6 +55,8 @@
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#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
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#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
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void __cvmx_interrupt_asxx_enable(int block);
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union cvmx_asxx_gmii_rx_clk_set {
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uint64_t u64;
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struct cvmx_asxx_gmii_rx_clk_set_s {
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -2070,6 +2070,8 @@ static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
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return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
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}
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void __cvmx_interrupt_gmxx_enable(int interface);
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union cvmx_gmxx_bad_reg {
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uint64_t u64;
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struct cvmx_gmxx_bad_reg_s {
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -334,6 +334,8 @@ static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsig
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return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
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}
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void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
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union cvmx_pcsx_anx_adv_reg {
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uint64_t u64;
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struct cvmx_pcsx_anx_adv_reg_s {
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -268,6 +268,8 @@ static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
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return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
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}
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void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
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union cvmx_pcsxx_10gbx_status_reg {
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uint64_t u64;
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struct cvmx_pcsxx_10gbx_status_reg_s {
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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@ -45,6 +45,8 @@
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#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
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void __cvmx_interrupt_spxx_int_msk_enable(int index);
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union cvmx_spxx_bckprs_cnt {
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uint64_t u64;
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struct cvmx_spxx_bckprs_cnt_s {
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@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
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void __cvmx_interrupt_stxx_int_msk_enable(int index);
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union cvmx_stxx_arb_ctl {
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uint64_t u64;
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struct cvmx_stxx_arb_ctl_s {
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@ -279,13 +279,12 @@ union octeon_cvmemctl {
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} s;
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};
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extern void octeon_write_lcd(const char *s);
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extern void octeon_check_cpu_bist(void);
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extern int octeon_get_boot_uart(void);
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struct uart_port;
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extern unsigned int octeon_serial_in(struct uart_port *, int);
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extern void octeon_serial_out(struct uart_port *, int, int);
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int octeon_prune_device_tree(void);
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extern const char __appended_dtb;
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extern const char __dtb_octeon_3xxx_begin;
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extern const char __dtb_octeon_68xx_begin;
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/**
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* Write a 32bit value to the Octeon NPI register space
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