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First set of Counter driver fixes for 6.3
This set consists of two fixes for the 104-quad-8 driver: - fix a read race condition between the FLAG and CNTR registers (as a result 25-bit count values are no longer supported) - invert condition check to report correct Index Synapse action -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCZBXAAQAKCRC1SFbKvhIj K3TqAP466wJc//OR1eB/nS74Otrz8tQUEw2VpK3yf5YTH9IZUAEAnZzz4/bIXZuA Ioy+lGQHwE0Ebu3efCUU+OQEWGPQtQo= =45BY -----END PGP SIGNATURE----- Merge tag 'counter-fixes-6.3a' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus William writes: First set of Counter driver fixes for 6.3 This set consists of two fixes for the 104-quad-8 driver: - fix a read race condition between the FLAG and CNTR registers (as a result 25-bit count values are no longer supported) - invert condition check to report correct Index Synapse action * tag 'counter-fixes-6.3a' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: 104-quad-8: Fix Synapse action reported for Index signals counter: 104-quad-8: Fix race condition between FLAG and CNTR reads
This commit is contained in:
commit
840525415b
1 changed files with 9 additions and 22 deletions
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@ -97,10 +97,6 @@ struct quad8 {
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struct quad8_reg __iomem *reg;
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};
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/* Borrow Toggle flip-flop */
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#define QUAD8_FLAG_BT BIT(0)
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/* Carry Toggle flip-flop */
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#define QUAD8_FLAG_CT BIT(1)
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/* Error flag */
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#define QUAD8_FLAG_E BIT(4)
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/* Up/Down flag */
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@ -133,6 +129,9 @@ struct quad8 {
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#define QUAD8_CMR_QUADRATURE_X2 0x10
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#define QUAD8_CMR_QUADRATURE_X4 0x18
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/* Each Counter is 24 bits wide */
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#define LS7267_CNTR_MAX GENMASK(23, 0)
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static int quad8_signal_read(struct counter_device *counter,
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struct counter_signal *signal,
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enum counter_signal_level *level)
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@ -156,18 +155,10 @@ static int quad8_count_read(struct counter_device *counter,
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{
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struct quad8 *const priv = counter_priv(counter);
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struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
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unsigned int flags;
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unsigned int borrow;
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unsigned int carry;
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unsigned long irqflags;
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int i;
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flags = ioread8(&chan->control);
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borrow = flags & QUAD8_FLAG_BT;
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carry = !!(flags & QUAD8_FLAG_CT);
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/* Borrow XOR Carry effectively doubles count range */
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*val = (unsigned long)(borrow ^ carry) << 24;
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*val = 0;
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spin_lock_irqsave(&priv->lock, irqflags);
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@ -191,8 +182,7 @@ static int quad8_count_write(struct counter_device *counter,
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unsigned long irqflags;
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int i;
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/* Only 24-bit values are supported */
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if (val > 0xFFFFFF)
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if (val > LS7267_CNTR_MAX)
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return -ERANGE;
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spin_lock_irqsave(&priv->lock, irqflags);
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@ -378,7 +368,7 @@ static int quad8_action_read(struct counter_device *counter,
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/* Handle Index signals */
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if (synapse->signal->id >= 16) {
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if (priv->preset_enable[count->id])
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if (!priv->preset_enable[count->id])
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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else
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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@ -806,8 +796,7 @@ static int quad8_count_preset_write(struct counter_device *counter,
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struct quad8 *const priv = counter_priv(counter);
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unsigned long irqflags;
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/* Only 24-bit values are supported */
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if (preset > 0xFFFFFF)
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if (preset > LS7267_CNTR_MAX)
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return -ERANGE;
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spin_lock_irqsave(&priv->lock, irqflags);
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@ -834,8 +823,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
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*ceiling = priv->preset[count->id];
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break;
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default:
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/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
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*ceiling = 0x1FFFFFF;
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*ceiling = LS7267_CNTR_MAX;
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break;
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}
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@ -850,8 +838,7 @@ static int quad8_count_ceiling_write(struct counter_device *counter,
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struct quad8 *const priv = counter_priv(counter);
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unsigned long irqflags;
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/* Only 24-bit values are supported */
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if (ceiling > 0xFFFFFF)
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if (ceiling > LS7267_CNTR_MAX)
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return -ERANGE;
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spin_lock_irqsave(&priv->lock, irqflags);
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