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dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
Convert Qualcomm ADSP/CDSP Remoteproc devicetree binding to YAML. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1643712724-12436-2-git-send-email-quic_mpubbise@quicinc.com
This commit is contained in:
Rakesh Pillai
Bjorn Andersson
parent
b843192039
commit
841fdd0ac0
3 changed files with 321 additions and 140 deletions
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@ -1,140 +0,0 @@
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Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader
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This document defines the binding for a component that loads and boots firmware
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on the Qualcomm Technology Inc. Hexagon v56 core.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,qcs404-cdsp-pil",
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"qcom,sdm845-adsp-pil"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must specify the base address and size of the qdsp6ss register
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- interrupts-extended:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must list the watchdog, fatal IRQs ready, handover and
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stop-ack IRQs
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- interrupt-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandles and clock specifier pairs for the Hexagon,
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per clock-names below.
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- clock-names:
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Usage: required for SDM845 ADSP
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Value type: <stringlist>
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Definition: List of clock input name strings sorted in the same
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order as the clocks property. Definition must have
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"xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",
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"lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
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and "qdsp6ss_core".
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- clock-names:
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Usage: required for QCS404 CDSP
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Value type: <stringlist>
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Definition: List of clock input name strings sorted in the same
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order as the clocks property. Definition must have
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"xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
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"q6ss_master", "q6_axim".
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- power-domains:
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Usage: required
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Value type: <phandle>
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Definition: reference to cx power domain node.
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- resets:
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Usage: required
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Value type: <phandle>
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Definition: reference to the list of resets for the Hexagon.
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- reset-names:
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Usage: required for SDM845 ADSP
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Value type: <stringlist>
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Definition: must be "pdc_sync" and "cc_lpass"
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- reset-names:
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Usage: required for QCS404 CDSP
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Value type: <stringlist>
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Definition: must be "restart"
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- qcom,halt-regs:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: a phandle reference to a syscon representing TCSR followed
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by the offset within syscon for Hexagon halt register.
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- memory-region:
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Usage: required
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Value type: <phandle>
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Definition: reference to the reserved-memory for the firmware
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- qcom,smem-states:
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Usage: required
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Value type: <phandle>
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Definition: reference to the smem state for requesting the Hexagon to
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shut down
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- qcom,smem-state-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "stop"
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= SUBNODES
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The adsp node may have an subnode named "glink-edge" that describes the
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communication edge, channels and devices related to the Hexagon.
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See ../soc/qcom/qcom,glink.txt for details on how to describe these.
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= EXAMPLE
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The following example describes the resources needed to boot control the
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ADSP, as it is found on SDM845 boards.
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remoteproc@17300000 {
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compatible = "qcom,sdm845-adsp-pil";
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reg = <0x17300000 0x40c>;
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_LPASS_SWAY_CLK>,
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<&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
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<&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
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<&lpasscc LPASS_QDSP6SS_XO_CLK>,
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<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
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<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
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clock-names = "xo", "sway_cbcr",
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"lpass_ahbs_aon_cbcr",
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"lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
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"qdsp6ss_sleep", "qdsp6ss_core";
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power-domains = <&rpmhpd SDM845_CX>;
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resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
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<&aoss_reset AOSS_CC_LPASS_RESTART>;
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reset-names = "pdc_sync", "cc_lpass";
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qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
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memory-region = <&pil_adsp_mem>;
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qcom,smem-states = <&adsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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};
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@ -0,0 +1,161 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QCS404 CDSP Peripheral Image Loader
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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This document defines the binding for a component that loads and boots firmware
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on the Qualcomm Technology Inc. CDSP (Compute DSP).
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properties:
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compatible:
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enum:
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- qcom,qcs404-cdsp-pil
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reg:
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maxItems: 1
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description:
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The base address and size of the qdsp6ss register
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interrupts:
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items:
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- description: Watchdog interrupt
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- description: Fatal interrupt
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- description: Ready interrupt
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- description: Handover interrupt
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- description: Stop acknowledge interrupt
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interrupt-names:
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items:
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- const: wdog
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- const: fatal
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- const: ready
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- const: handover
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- const: stop-ack
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clocks:
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items:
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- description: XO clock
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- description: SWAY clock
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- description: TBU clock
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- description: BIMC clock
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- description: AHB AON clock
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- description: Q6SS SLAVE clock
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- description: Q6SS MASTER clock
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- description: Q6 AXIM clock
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clock-names:
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items:
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- const: xo
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- const: sway
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- const: tbu
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- const: bimc
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- const: ahb_aon
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- const: q6ss_slave
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- const: q6ss_master
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- const: q6_axim
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power-domains:
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items:
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- description: CX power domain
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resets:
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items:
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- description: AOSS restart
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reset-names:
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items:
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- const: restart
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memory-region:
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maxItems: 1
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description: Reference to the reserved-memory for the Hexagon core
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qcom,halt-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Phandle reference to a syscon representing TCSR followed by the
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three offsets within syscon for q6, modem and nc halt registers.
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qcom,smem-states:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: States used by the AP to signal the Hexagon core
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items:
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- description: Stop the modem
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qcom,smem-state-names:
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$ref: /schemas/types.yaml#/definitions/string
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description: The names of the state bits used for SMP2P output
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items:
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- const: stop
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- power-domains
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- resets
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- reset-names
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- qcom,halt-regs
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- memory-region
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- qcom,smem-states
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- qcom,smem-state-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
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remoteproc@b00000 {
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compatible = "qcom,qcs404-cdsp-pil";
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reg = <0x00b00000 0x4040>;
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interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&xo_board>,
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<&gcc GCC_CDSP_CFG_AHB_CLK>,
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<&gcc GCC_CDSP_TBU_CLK>,
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<&gcc GCC_BIMC_CDSP_CLK>,
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<&turingcc TURING_WRAPPER_AON_CLK>,
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<&turingcc TURING_Q6SS_AHBS_AON_CLK>,
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<&turingcc TURING_Q6SS_AHBM_AON_CLK>,
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<&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
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clock-names = "xo",
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"sway",
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"tbu",
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"bimc",
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"ahb_aon",
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"q6ss_slave",
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"q6ss_master",
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"q6_axim";
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power-domains = <&rpmhpd SDM845_CX>;
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resets = <&gcc GCC_CDSP_RESTART>;
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reset-names = "restart";
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qcom,halt-regs = <&tcsr 0x19004>;
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memory-region = <&cdsp_fw_mem>;
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qcom,smem-states = <&cdsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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};
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@ -0,0 +1,160 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM845 ADSP Peripheral Image Loader
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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This document defines the binding for a component that loads and boots firmware
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on the Qualcomm Technology Inc. ADSP.
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properties:
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compatible:
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enum:
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- qcom,sdm845-adsp-pil
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reg:
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maxItems: 1
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description:
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The base address and size of the qdsp6ss register
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interrupts:
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items:
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- description: Watchdog interrupt
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- description: Fatal interrupt
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- description: Ready interrupt
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- description: Handover interrupt
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- description: Stop acknowledge interrupt
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interrupt-names:
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items:
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- const: wdog
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- const: fatal
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- const: ready
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- const: handover
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- const: stop-ack
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clocks:
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items:
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- description: XO clock
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- description: SWAY clock
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- description: LPASS AHBS AON clock
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- description: LPASS AHBM AON clock
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- description: QDSP XO clock
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- description: Q6SP6SS SLEEP clock
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- description: Q6SP6SS CORE clock
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clock-names:
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items:
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- const: xo
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- const: sway_cbcr
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- const: lpass_ahbs_aon_cbcr
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- const: lpass_ahbm_aon_cbcr
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- const: qdsp6ss_xo
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- const: qdsp6ss_sleep
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- const: qdsp6ss_core
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power-domains:
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items:
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- description: CX power domain
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resets:
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items:
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- description: PDC AUDIO SYNC RESET
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- description: CC LPASS restart
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reset-names:
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items:
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- const: pdc_sync
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- const: cc_lpass
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memory-region:
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maxItems: 1
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description: Reference to the reserved-memory for the Hexagon core
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qcom,halt-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Phandle reference to a syscon representing TCSR followed by the
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three offsets within syscon for q6, modem and nc halt registers.
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|
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qcom,smem-states:
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$ref: /schemas/types.yaml#/definitions/phandle-array
|
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description: States used by the AP to signal the Hexagon core
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items:
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- description: Stop the modem
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||||
|
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qcom,smem-state-names:
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$ref: /schemas/types.yaml#/definitions/string
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description: The names of the state bits used for SMP2P output
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items:
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- const: stop
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required:
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||||
- compatible
|
||||
- reg
|
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- interrupts
|
||||
- interrupt-names
|
||||
- clocks
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||||
- clock-names
|
||||
- power-domains
|
||||
- resets
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||||
- reset-names
|
||||
- qcom,halt-regs
|
||||
- memory-region
|
||||
- qcom,smem-states
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||||
- qcom,smem-state-names
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additionalProperties: false
|
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,lpass-sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/reset/qcom,sdm845-pdc.h>
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#include <dt-bindings/reset/qcom,sdm845-aoss.h>
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remoteproc@17300000 {
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compatible = "qcom,sdm845-adsp-pil";
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reg = <0x17300000 0x40c>;
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_LPASS_SWAY_CLK>,
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<&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
|
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<&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
|
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<&lpasscc LPASS_QDSP6SS_XO_CLK>,
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<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
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<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
|
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clock-names = "xo", "sway_cbcr",
|
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"lpass_ahbs_aon_cbcr",
|
||||
"lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
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"qdsp6ss_sleep", "qdsp6ss_core";
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||||
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power-domains = <&rpmhpd SDM845_CX>;
|
||||
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||||
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
|
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<&aoss_reset AOSS_CC_LPASS_RESTART>;
|
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reset-names = "pdc_sync", "cc_lpass";
|
||||
|
||||
qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
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||||
|
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memory-region = <&pil_adsp_mem>;
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||||
|
||||
qcom,smem-states = <&adsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
};
|
||||
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Reference in a new issue