mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
John W. Linville says: ==================== pull request: wireless 2013-11-14 Please pull this batch of fixes intended for the 3.13 stream! Amitkumar Karwar offers a quartet of mwifiex fixes, including an endian fix and three fixes for invalid memory access. Avinash Patil trims the packet length value for packets received from an SDIO interface. Colin Ian King fixes a NULL pointer dereference in the rtlwifi efuse code. Dan Carpenter cleans-up an mwifiex integer underflow, a potential libertas oops, a memory corrupion bug in wcn36xx, and a locking issue also in wcn36xx. Dan Williams helps prism54 devices to avoid being misclassified as Ethernet devices. Felipe Pena fixes a couple of typo errors, one in rt2x00 and the other in rtlwifi. Janusz Dziedzic corrects a pair of DFS-related problems in ath9k. Larry Finger patches three rtlwifi drivers to correctly report signal strength even for an unassociated AP. Mark Cave-Ayland rewrites some endian-illiterate packet type extraction code in rtlwifi. Stanislaw Gruszka addresses an rt2x00 regression related to setting HT station WCID and AMPDU density parameters. Sujith Manoharan corrects the initvals settings for AR9485. Ujjal Roy patches an obscure bit of code in mwifiex that was using the wrong definition of eth_hdr when briding patches in AP mode. Wei Yongjun fixes a couple of bugs: one is a return code handling bug in libertas; and, the other is a locking issue in wcn36xx. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
8422d1f181
31 changed files with 283 additions and 162 deletions
|
@ -187,17 +187,17 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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if (ah->config.no_pll_pwrsave) {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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} else {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
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}
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} else if (AR_SREV_9462_21(ah)) {
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9462_2p1_mac_core);
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@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postamble[][5] = {
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{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
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};
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static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18012e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
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/* Addr allmodes */
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{0x00009e00, 0x037216a0},
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@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
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{0x0000a1fc, 0x00000296},
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};
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static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18052e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18053e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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static const u32 ar9485_1_1_soc_preamble[][2] = {
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/* Addr allmodes */
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{0x00004014, 0xba280400},
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@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = {
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{0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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};
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static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18013e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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static const u32 ar9485_1_1_radio_postamble[][2] = {
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/* Addr allmodes */
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{0x0001609c, 0x0b283f31},
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@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
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{0x0000a3a0, 0xca9228ee},
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};
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static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18013e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x1801265e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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#endif /* INITVALS_9485_H */
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|
|
|
@ -632,15 +632,16 @@ void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
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/* Main driver core */
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/********************/
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#define ATH9K_PCI_CUS198 0x0001
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#define ATH9K_PCI_CUS230 0x0002
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#define ATH9K_PCI_CUS217 0x0004
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#define ATH9K_PCI_CUS252 0x0008
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#define ATH9K_PCI_WOW 0x0010
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#define ATH9K_PCI_BT_ANT_DIV 0x0020
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#define ATH9K_PCI_D3_L1_WAR 0x0040
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#define ATH9K_PCI_AR9565_1ANT 0x0080
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#define ATH9K_PCI_AR9565_2ANT 0x0100
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#define ATH9K_PCI_CUS198 0x0001
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#define ATH9K_PCI_CUS230 0x0002
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#define ATH9K_PCI_CUS217 0x0004
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#define ATH9K_PCI_CUS252 0x0008
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#define ATH9K_PCI_WOW 0x0010
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#define ATH9K_PCI_BT_ANT_DIV 0x0020
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#define ATH9K_PCI_D3_L1_WAR 0x0040
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#define ATH9K_PCI_AR9565_1ANT 0x0080
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#define ATH9K_PCI_AR9565_2ANT 0x0100
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#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
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/*
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* Default cache line size, in bytes.
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|
|
|
@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file *file, char __user *user_buf,
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|||
if (buf == NULL)
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return -ENOMEM;
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if (sc->dfs_detector)
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dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
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len += scnprintf(buf + len, size - len, "DFS support for "
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"macVersion = 0x%x, macRev = 0x%x: %s\n",
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hw_ver->macVersion, hw_ver->macRev,
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(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
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"enabled" : "disabled");
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if (!sc->dfs_detector) {
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len += scnprintf(buf + len, size - len,
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"DFS detector not enabled\n");
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goto exit;
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}
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dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
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len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
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ATH9K_DFS_STAT("pulse events reported ", pulses_total);
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ATH9K_DFS_STAT("invalid pulse events ", pulses_no_dfs);
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@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file *file, char __user *user_buf,
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ATH9K_DFS_POOL_STAT("Seqs. alloc error ", pseq_alloc_error);
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ATH9K_DFS_POOL_STAT("Seqs. in use ", pseq_used);
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exit:
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if (len > size)
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len = size;
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|
|
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@ -316,6 +316,7 @@ struct ath9k_ops_config {
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u32 ant_ctrl_comm2g_switch_enable;
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bool xatten_margin_cfg;
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bool alt_mingainidx;
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bool no_pll_pwrsave;
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};
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enum ath9k_int {
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|
|
|
@ -609,6 +609,11 @@ static void ath9k_init_platform(struct ath_softc *sc)
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ah->config.pcie_waen = 0x0040473b;
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ath_info(common, "Enable WAR for ASPM D3/L1\n");
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}
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if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
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ah->config.no_pll_pwrsave = true;
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ath_info(common, "Disable PLL PowerSave\n");
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}
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}
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static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
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|
@ -863,8 +868,8 @@ static const struct ieee80211_iface_combination if_comb[] = {
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.max_interfaces = 1,
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.num_different_channels = 1,
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.beacon_int_infra_match = true,
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.radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
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BIT(NL80211_CHAN_HT20),
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.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
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BIT(NL80211_CHAN_WIDTH_20),
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}
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};
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|
||||
|
|
|
@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
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0x3219),
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.driver_data = ATH9K_PCI_BT_ANT_DIV },
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|
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/* AR9485 cards with PLL power-save disabled by default. */
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
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0x0032,
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PCI_VENDOR_ID_AZWAVE,
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0x2C97),
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.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
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0x0032,
|
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PCI_VENDOR_ID_AZWAVE,
|
||||
0x2100),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
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0x0032,
|
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0x1C56, /* ASKEY */
|
||||
0x4001),
|
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.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
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{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
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0x0032,
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0x11AD, /* LITEON */
|
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0x6627),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x11AD, /* LITEON */
|
||||
0x6628),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_FOXCONN,
|
||||
0xE04E),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_FOXCONN,
|
||||
0xE04F),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x144F, /* ASKEY */
|
||||
0x7197),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x1B9A, /* XAVI */
|
||||
0x2000),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x1B9A, /* XAVI */
|
||||
0x2001),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_AZWAVE,
|
||||
0x1186),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_AZWAVE,
|
||||
0x1F86),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_AZWAVE,
|
||||
0x1195),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_AZWAVE,
|
||||
0x1F95),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x1B9A, /* XAVI */
|
||||
0x1C00),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
0x1B9A, /* XAVI */
|
||||
0x1C01),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
|
||||
0x0032,
|
||||
PCI_VENDOR_ID_ASUSTEK,
|
||||
0x850D),
|
||||
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
|
||||
|
||||
{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
|
||||
{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
|
||||
|
||||
|
|
|
@ -126,7 +126,7 @@ static ssize_t write_file_dump(struct file *file,
|
|||
if (begin == NULL)
|
||||
break;
|
||||
|
||||
if (kstrtoul(begin, 0, (unsigned long *)(arg + i)) != 0)
|
||||
if (kstrtou32(begin, 0, &arg[i]) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -1286,7 +1286,8 @@ int wcn36xx_smd_send_beacon(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
} else {
|
||||
wcn36xx_err("Beacon is to big: beacon size=%d\n",
|
||||
msg_body.beacon_length);
|
||||
return -ENOMEM;
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
memcpy(msg_body.bssid, vif->addr, ETH_ALEN);
|
||||
|
||||
|
@ -1327,7 +1328,8 @@ int wcn36xx_smd_update_proberesp_tmpl(struct wcn36xx *wcn,
|
|||
if (skb->len > BEACON_TEMPLATE_SIZE) {
|
||||
wcn36xx_warn("probe response template is too big: %d\n",
|
||||
skb->len);
|
||||
return -E2BIG;
|
||||
ret = -E2BIG;
|
||||
goto out;
|
||||
}
|
||||
|
||||
msg.probe_resp_template_len = skb->len;
|
||||
|
@ -1606,7 +1608,8 @@ int wcn36xx_smd_keep_alive_req(struct wcn36xx *wcn,
|
|||
/* TODO: it also support ARP response type */
|
||||
} else {
|
||||
wcn36xx_warn("unknow keep alive packet type %d\n", packet_type);
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
|
|
@ -913,7 +913,10 @@ static ssize_t lbs_debugfs_write(struct file *f, const char __user *buf,
|
|||
char *p2;
|
||||
struct debug_data *d = f->private_data;
|
||||
|
||||
pdata = kmalloc(cnt, GFP_KERNEL);
|
||||
if (cnt == 0)
|
||||
return 0;
|
||||
|
||||
pdata = kmalloc(cnt + 1, GFP_KERNEL);
|
||||
if (pdata == NULL)
|
||||
return 0;
|
||||
|
||||
|
@ -922,6 +925,7 @@ static ssize_t lbs_debugfs_write(struct file *f, const char __user *buf,
|
|||
kfree(pdata);
|
||||
return 0;
|
||||
}
|
||||
pdata[cnt] = '\0';
|
||||
|
||||
p0 = pdata;
|
||||
for (i = 0; i < num_of_items; i++) {
|
||||
|
|
|
@ -902,6 +902,7 @@ static int if_cs_probe(struct pcmcia_device *p_dev)
|
|||
if (card->model == MODEL_UNKNOWN) {
|
||||
pr_err("unsupported manf_id 0x%04x / card_id 0x%04x\n",
|
||||
p_dev->manf_id, p_dev->card_id);
|
||||
ret = -ENODEV;
|
||||
goto out2;
|
||||
}
|
||||
|
||||
|
|
|
@ -1020,8 +1020,8 @@ struct mwifiex_power_group {
|
|||
} __packed;
|
||||
|
||||
struct mwifiex_types_power_group {
|
||||
u16 type;
|
||||
u16 length;
|
||||
__le16 type;
|
||||
__le16 length;
|
||||
} __packed;
|
||||
|
||||
struct host_cmd_ds_txpwr_cfg {
|
||||
|
|
|
@ -82,7 +82,7 @@ mwifiex_update_autoindex_ies(struct mwifiex_private *priv,
|
|||
struct mwifiex_ie_list *ie_list)
|
||||
{
|
||||
u16 travel_len, index, mask;
|
||||
s16 input_len;
|
||||
s16 input_len, tlv_len;
|
||||
struct mwifiex_ie *ie;
|
||||
u8 *tmp;
|
||||
|
||||
|
@ -91,11 +91,13 @@ mwifiex_update_autoindex_ies(struct mwifiex_private *priv,
|
|||
|
||||
ie_list->len = 0;
|
||||
|
||||
while (input_len > 0) {
|
||||
while (input_len >= sizeof(struct mwifiex_ie_types_header)) {
|
||||
ie = (struct mwifiex_ie *)(((u8 *)ie_list) + travel_len);
|
||||
input_len -= le16_to_cpu(ie->ie_length) + MWIFIEX_IE_HDR_SIZE;
|
||||
travel_len += le16_to_cpu(ie->ie_length) + MWIFIEX_IE_HDR_SIZE;
|
||||
tlv_len = le16_to_cpu(ie->ie_length);
|
||||
travel_len += tlv_len + MWIFIEX_IE_HDR_SIZE;
|
||||
|
||||
if (input_len < tlv_len + MWIFIEX_IE_HDR_SIZE)
|
||||
return -1;
|
||||
index = le16_to_cpu(ie->ie_index);
|
||||
mask = le16_to_cpu(ie->mgmt_subtype_mask);
|
||||
|
||||
|
@ -132,6 +134,7 @@ mwifiex_update_autoindex_ies(struct mwifiex_private *priv,
|
|||
le16_add_cpu(&ie_list->len,
|
||||
le16_to_cpu(priv->mgmt_ie[index].ie_length) +
|
||||
MWIFIEX_IE_HDR_SIZE);
|
||||
input_len -= tlv_len + MWIFIEX_IE_HDR_SIZE;
|
||||
}
|
||||
|
||||
if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_UAP)
|
||||
|
|
|
@ -1029,7 +1029,10 @@ static int mwifiex_decode_rx_packet(struct mwifiex_adapter *adapter,
|
|||
struct sk_buff *skb, u32 upld_typ)
|
||||
{
|
||||
u8 *cmd_buf;
|
||||
__le16 *curr_ptr = (__le16 *)skb->data;
|
||||
u16 pkt_len = le16_to_cpu(*curr_ptr);
|
||||
|
||||
skb_trim(skb, pkt_len);
|
||||
skb_pull(skb, INTF_HEADER_LEN);
|
||||
|
||||
switch (upld_typ) {
|
||||
|
|
|
@ -239,14 +239,14 @@ static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
|
|||
memmove(cmd_txp_cfg, txp,
|
||||
sizeof(struct host_cmd_ds_txpwr_cfg) +
|
||||
sizeof(struct mwifiex_types_power_group) +
|
||||
pg_tlv->length);
|
||||
le16_to_cpu(pg_tlv->length));
|
||||
|
||||
pg_tlv = (struct mwifiex_types_power_group *) ((u8 *)
|
||||
cmd_txp_cfg +
|
||||
sizeof(struct host_cmd_ds_txpwr_cfg));
|
||||
cmd->size = cpu_to_le16(le16_to_cpu(cmd->size) +
|
||||
sizeof(struct mwifiex_types_power_group) +
|
||||
pg_tlv->length);
|
||||
le16_to_cpu(pg_tlv->length));
|
||||
} else {
|
||||
memmove(cmd_txp_cfg, txp, sizeof(*txp));
|
||||
}
|
||||
|
|
|
@ -274,17 +274,20 @@ static int mwifiex_ret_tx_rate_cfg(struct mwifiex_private *priv,
|
|||
struct host_cmd_ds_tx_rate_cfg *rate_cfg = &resp->params.tx_rate_cfg;
|
||||
struct mwifiex_rate_scope *rate_scope;
|
||||
struct mwifiex_ie_types_header *head;
|
||||
u16 tlv, tlv_buf_len;
|
||||
u16 tlv, tlv_buf_len, tlv_buf_left;
|
||||
u8 *tlv_buf;
|
||||
u32 i;
|
||||
|
||||
tlv_buf = ((u8 *)rate_cfg) +
|
||||
sizeof(struct host_cmd_ds_tx_rate_cfg);
|
||||
tlv_buf_len = le16_to_cpu(*(__le16 *) (tlv_buf + sizeof(u16)));
|
||||
tlv_buf = ((u8 *)rate_cfg) + sizeof(struct host_cmd_ds_tx_rate_cfg);
|
||||
tlv_buf_left = le16_to_cpu(resp->size) - S_DS_GEN - sizeof(*rate_cfg);
|
||||
|
||||
while (tlv_buf && tlv_buf_len > 0) {
|
||||
tlv = (*tlv_buf);
|
||||
tlv = tlv | (*(tlv_buf + 1) << 8);
|
||||
while (tlv_buf_left >= sizeof(*head)) {
|
||||
head = (struct mwifiex_ie_types_header *)tlv_buf;
|
||||
tlv = le16_to_cpu(head->type);
|
||||
tlv_buf_len = le16_to_cpu(head->len);
|
||||
|
||||
if (tlv_buf_left < (sizeof(*head) + tlv_buf_len))
|
||||
break;
|
||||
|
||||
switch (tlv) {
|
||||
case TLV_TYPE_RATE_SCOPE:
|
||||
|
@ -304,9 +307,8 @@ static int mwifiex_ret_tx_rate_cfg(struct mwifiex_private *priv,
|
|||
/* Add RATE_DROP tlv here */
|
||||
}
|
||||
|
||||
head = (struct mwifiex_ie_types_header *) tlv_buf;
|
||||
tlv_buf += le16_to_cpu(head->len) + sizeof(*head);
|
||||
tlv_buf_len -= le16_to_cpu(head->len);
|
||||
tlv_buf += (sizeof(*head) + tlv_buf_len);
|
||||
tlv_buf_left -= (sizeof(*head) + tlv_buf_len);
|
||||
}
|
||||
|
||||
priv->is_data_rate_auto = mwifiex_is_rate_auto(priv);
|
||||
|
@ -340,13 +342,17 @@ static int mwifiex_get_power_level(struct mwifiex_private *priv, void *data_buf)
|
|||
((u8 *) data_buf + sizeof(struct host_cmd_ds_txpwr_cfg));
|
||||
pg = (struct mwifiex_power_group *)
|
||||
((u8 *) pg_tlv_hdr + sizeof(struct mwifiex_types_power_group));
|
||||
length = pg_tlv_hdr->length;
|
||||
if (length > 0) {
|
||||
max_power = pg->power_max;
|
||||
min_power = pg->power_min;
|
||||
length -= sizeof(struct mwifiex_power_group);
|
||||
}
|
||||
while (length) {
|
||||
length = le16_to_cpu(pg_tlv_hdr->length);
|
||||
|
||||
/* At least one structure required to update power */
|
||||
if (length < sizeof(struct mwifiex_power_group))
|
||||
return 0;
|
||||
|
||||
max_power = pg->power_max;
|
||||
min_power = pg->power_min;
|
||||
length -= sizeof(struct mwifiex_power_group);
|
||||
|
||||
while (length >= sizeof(struct mwifiex_power_group)) {
|
||||
pg++;
|
||||
if (max_power < pg->power_max)
|
||||
max_power = pg->power_max;
|
||||
|
@ -356,10 +362,8 @@ static int mwifiex_get_power_level(struct mwifiex_private *priv, void *data_buf)
|
|||
|
||||
length -= sizeof(struct mwifiex_power_group);
|
||||
}
|
||||
if (pg_tlv_hdr->length > 0) {
|
||||
priv->min_tx_power_level = (u8) min_power;
|
||||
priv->max_tx_power_level = (u8) max_power;
|
||||
}
|
||||
priv->min_tx_power_level = (u8) min_power;
|
||||
priv->max_tx_power_level = (u8) max_power;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -638,8 +638,9 @@ int mwifiex_set_tx_power(struct mwifiex_private *priv,
|
|||
txp_cfg->mode = cpu_to_le32(1);
|
||||
pg_tlv = (struct mwifiex_types_power_group *)
|
||||
(buf + sizeof(struct host_cmd_ds_txpwr_cfg));
|
||||
pg_tlv->type = TLV_TYPE_POWER_GROUP;
|
||||
pg_tlv->length = 4 * sizeof(struct mwifiex_power_group);
|
||||
pg_tlv->type = cpu_to_le16(TLV_TYPE_POWER_GROUP);
|
||||
pg_tlv->length =
|
||||
cpu_to_le16(4 * sizeof(struct mwifiex_power_group));
|
||||
pg = (struct mwifiex_power_group *)
|
||||
(buf + sizeof(struct host_cmd_ds_txpwr_cfg)
|
||||
+ sizeof(struct mwifiex_types_power_group));
|
||||
|
|
|
@ -97,6 +97,7 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
struct mwifiex_txinfo *tx_info;
|
||||
int hdr_chop;
|
||||
struct timeval tv;
|
||||
struct ethhdr *p_ethhdr;
|
||||
u8 rfc1042_eth_hdr[ETH_ALEN] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
|
||||
|
||||
uap_rx_pd = (struct uap_rxpd *)(skb->data);
|
||||
|
@ -112,14 +113,36 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
}
|
||||
|
||||
if (!memcmp(&rx_pkt_hdr->rfc1042_hdr,
|
||||
rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr)))
|
||||
rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr))) {
|
||||
/* Replace the 803 header and rfc1042 header (llc/snap) with
|
||||
* an Ethernet II header, keep the src/dst and snap_type
|
||||
* (ethertype).
|
||||
*
|
||||
* The firmware only passes up SNAP frames converting all RX
|
||||
* data from 802.11 to 802.2/LLC/SNAP frames.
|
||||
*
|
||||
* To create the Ethernet II, just move the src, dst address
|
||||
* right before the snap_type.
|
||||
*/
|
||||
p_ethhdr = (struct ethhdr *)
|
||||
((u8 *)(&rx_pkt_hdr->eth803_hdr)
|
||||
+ sizeof(rx_pkt_hdr->eth803_hdr)
|
||||
+ sizeof(rx_pkt_hdr->rfc1042_hdr)
|
||||
- sizeof(rx_pkt_hdr->eth803_hdr.h_dest)
|
||||
- sizeof(rx_pkt_hdr->eth803_hdr.h_source)
|
||||
- sizeof(rx_pkt_hdr->rfc1042_hdr.snap_type));
|
||||
memcpy(p_ethhdr->h_source, rx_pkt_hdr->eth803_hdr.h_source,
|
||||
sizeof(p_ethhdr->h_source));
|
||||
memcpy(p_ethhdr->h_dest, rx_pkt_hdr->eth803_hdr.h_dest,
|
||||
sizeof(p_ethhdr->h_dest));
|
||||
/* Chop off the rxpd + the excess memory from
|
||||
* 802.2/llc/snap header that was removed.
|
||||
*/
|
||||
hdr_chop = (u8 *)eth_hdr - (u8 *)uap_rx_pd;
|
||||
else
|
||||
hdr_chop = (u8 *)p_ethhdr - (u8 *)uap_rx_pd;
|
||||
} else {
|
||||
/* Chop off the rxpd */
|
||||
hdr_chop = (u8 *)&rx_pkt_hdr->eth803_hdr - (u8 *)uap_rx_pd;
|
||||
}
|
||||
|
||||
/* Chop off the leading header bytes so the it points
|
||||
* to the start of either the reconstructed EthII frame
|
||||
|
|
|
@ -722,6 +722,9 @@ int mwifiex_ret_wmm_get_status(struct mwifiex_private *priv,
|
|||
tlv_hdr = (struct mwifiex_ie_types_data *) curr;
|
||||
tlv_len = le16_to_cpu(tlv_hdr->header.len);
|
||||
|
||||
if (resp_len < tlv_len + sizeof(tlv_hdr->header))
|
||||
break;
|
||||
|
||||
switch (le16_to_cpu(tlv_hdr->header.type)) {
|
||||
case TLV_TYPE_WMMQSTATUS:
|
||||
tlv_wmm_qstatus =
|
||||
|
|
|
@ -811,6 +811,10 @@ static const struct net_device_ops islpci_netdev_ops = {
|
|||
.ndo_validate_addr = eth_validate_addr,
|
||||
};
|
||||
|
||||
static struct device_type wlan_type = {
|
||||
.name = "wlan",
|
||||
};
|
||||
|
||||
struct net_device *
|
||||
islpci_setup(struct pci_dev *pdev)
|
||||
{
|
||||
|
@ -821,9 +825,8 @@ islpci_setup(struct pci_dev *pdev)
|
|||
return ndev;
|
||||
|
||||
pci_set_drvdata(pdev, ndev);
|
||||
#if defined(SET_NETDEV_DEV)
|
||||
SET_NETDEV_DEV(ndev, &pdev->dev);
|
||||
#endif
|
||||
SET_NETDEV_DEVTYPE(ndev, &wlan_type);
|
||||
|
||||
/* setup the structure members */
|
||||
ndev->base_addr = pci_resource_start(pdev, 0);
|
||||
|
|
|
@ -2640,7 +2640,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
|
|||
|
||||
if (rt2x00_rt(rt2x00dev, RT5392)) {
|
||||
rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
|
||||
if (info->default_power1 > POWER_BOUND)
|
||||
if (info->default_power2 > POWER_BOUND)
|
||||
rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
|
||||
else
|
||||
rt2x00_set_field8(&rfcsr, RFCSR50_TX,
|
||||
|
|
|
@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length);
|
|||
* @local: frame is not from mac80211
|
||||
*/
|
||||
int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
|
||||
bool local);
|
||||
struct ieee80211_sta *sta, bool local);
|
||||
|
||||
/**
|
||||
* rt2x00queue_update_beacon - Send new beacon from mac80211
|
||||
|
|
|
@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
|
|||
frag_skb->data, data_length, tx_info,
|
||||
(struct ieee80211_rts *)(skb->data));
|
||||
|
||||
retval = rt2x00queue_write_tx_frame(queue, skb, true);
|
||||
retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
|
||||
if (retval) {
|
||||
dev_kfree_skb_any(skb);
|
||||
rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
|
||||
|
@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *hw,
|
|||
goto exit_fail;
|
||||
}
|
||||
|
||||
if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
|
||||
if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
|
||||
goto exit_fail;
|
||||
|
||||
/*
|
||||
|
|
|
@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct queue_entry *entry)
|
|||
}
|
||||
|
||||
int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
|
||||
bool local)
|
||||
struct ieee80211_sta *sta, bool local)
|
||||
{
|
||||
struct ieee80211_tx_info *tx_info;
|
||||
struct queue_entry *entry;
|
||||
|
@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
|
|||
* after that we are free to use the skb->cb array
|
||||
* for our information.
|
||||
*/
|
||||
rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
|
||||
rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
|
||||
|
||||
/*
|
||||
* All information is retrieved from the skb->cb array,
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
|
||||
#include <linux/ip.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/udp.h>
|
||||
|
||||
/*
|
||||
*NOTICE!!!: This file will be very big, we should
|
||||
|
@ -1074,64 +1075,52 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
|
|||
if (!ieee80211_is_data(fc))
|
||||
return false;
|
||||
|
||||
ip = (const struct iphdr *)(skb->data + mac_hdr_len +
|
||||
SNAP_SIZE + PROTOC_TYPE_SIZE);
|
||||
ether_type = be16_to_cpup((__be16 *)
|
||||
(skb->data + mac_hdr_len + SNAP_SIZE));
|
||||
|
||||
ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
|
||||
SNAP_SIZE + PROTOC_TYPE_SIZE);
|
||||
ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
|
||||
/* ether_type = ntohs(ether_type); */
|
||||
switch (ether_type) {
|
||||
case ETH_P_IP: {
|
||||
struct udphdr *udp;
|
||||
u16 src;
|
||||
u16 dst;
|
||||
|
||||
if (ETH_P_IP == ether_type) {
|
||||
if (IPPROTO_UDP == ip->protocol) {
|
||||
struct udphdr *udp = (struct udphdr *)((u8 *) ip +
|
||||
(ip->ihl << 2));
|
||||
if (((((u8 *) udp)[1] == 68) &&
|
||||
(((u8 *) udp)[3] == 67)) ||
|
||||
((((u8 *) udp)[1] == 67) &&
|
||||
(((u8 *) udp)[3] == 68))) {
|
||||
/*
|
||||
* 68 : UDP BOOTP client
|
||||
* 67 : UDP BOOTP server
|
||||
*/
|
||||
RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV),
|
||||
DBG_DMESG, "dhcp %s !!\n",
|
||||
is_tx ? "Tx" : "Rx");
|
||||
if (ip->protocol != IPPROTO_UDP)
|
||||
return false;
|
||||
udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
|
||||
src = be16_to_cpu(udp->source);
|
||||
dst = be16_to_cpu(udp->dest);
|
||||
|
||||
if (is_tx) {
|
||||
rtlpriv->enter_ps = false;
|
||||
schedule_work(&rtlpriv->
|
||||
works.lps_change_work);
|
||||
ppsc->last_delaylps_stamp_jiffies =
|
||||
jiffies;
|
||||
}
|
||||
/* If this case involves port 68 (UDP BOOTP client) connecting
|
||||
* with port 67 (UDP BOOTP server), then return true so that
|
||||
* the lowest speed is used.
|
||||
*/
|
||||
if (!((src == 68 && dst == 67) || (src == 67 && dst == 68)))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
} else if (ETH_P_ARP == ether_type) {
|
||||
if (is_tx) {
|
||||
rtlpriv->enter_ps = false;
|
||||
schedule_work(&rtlpriv->works.lps_change_work);
|
||||
ppsc->last_delaylps_stamp_jiffies = jiffies;
|
||||
}
|
||||
|
||||
return true;
|
||||
} else if (ETH_P_PAE == ether_type) {
|
||||
RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
|
||||
"dhcp %s !!\n", is_tx ? "Tx" : "Rx");
|
||||
break;
|
||||
}
|
||||
case ETH_P_ARP:
|
||||
break;
|
||||
case ETH_P_PAE:
|
||||
RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
|
||||
"802.1X %s EAPOL pkt!!\n", is_tx ? "Tx" : "Rx");
|
||||
|
||||
if (is_tx) {
|
||||
rtlpriv->enter_ps = false;
|
||||
schedule_work(&rtlpriv->works.lps_change_work);
|
||||
ppsc->last_delaylps_stamp_jiffies = jiffies;
|
||||
}
|
||||
|
||||
return true;
|
||||
} else if (ETH_P_IPV6 == ether_type) {
|
||||
/* IPv6 */
|
||||
return true;
|
||||
break;
|
||||
case ETH_P_IPV6:
|
||||
/* TODO: Is this right? */
|
||||
return false;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
return false;
|
||||
if (is_tx) {
|
||||
rtlpriv->enter_ps = false;
|
||||
schedule_work(&rtlpriv->works.lps_change_work);
|
||||
ppsc->last_delaylps_stamp_jiffies = jiffies;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rtl_is_special_data);
|
||||
|
||||
|
|
|
@ -262,9 +262,9 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
|
|||
sizeof(u8), GFP_ATOMIC);
|
||||
if (!efuse_tbl)
|
||||
return;
|
||||
efuse_word = kmalloc(EFUSE_MAX_WORD_UNIT * sizeof(u16 *), GFP_ATOMIC);
|
||||
efuse_word = kzalloc(EFUSE_MAX_WORD_UNIT * sizeof(u16 *), GFP_ATOMIC);
|
||||
if (!efuse_word)
|
||||
goto done;
|
||||
goto out;
|
||||
for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
|
||||
efuse_word[i] = kmalloc(efuse_max_section * sizeof(u16),
|
||||
GFP_ATOMIC);
|
||||
|
@ -378,6 +378,7 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
|
|||
for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++)
|
||||
kfree(efuse_word[i]);
|
||||
kfree(efuse_word);
|
||||
out:
|
||||
kfree(efuse_tbl);
|
||||
}
|
||||
|
||||
|
|
|
@ -349,7 +349,7 @@ bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
|
|||
p_drvinfo);
|
||||
}
|
||||
/*rx_status->qual = stats->signal; */
|
||||
rx_status->signal = stats->rssi + 10;
|
||||
rx_status->signal = stats->recvsignalpower + 10;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
@ -525,7 +525,7 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
|
|||
p_drvinfo);
|
||||
}
|
||||
/*rx_status->qual = stats->signal; */
|
||||
rx_status->signal = stats->rssi + 10;
|
||||
rx_status->signal = stats->recvsignalpower + 10;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
@ -265,7 +265,7 @@ static void _rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw *hw,
|
|||
rtlefuse->pwrgroup_ht40
|
||||
[RF90_PATH_A][chnl - 1]) {
|
||||
pwrdiff_limit[i] =
|
||||
rtlefuse->pwrgroup_ht20
|
||||
rtlefuse->pwrgroup_ht40
|
||||
[RF90_PATH_A][chnl - 1];
|
||||
}
|
||||
} else {
|
||||
|
|
|
@ -329,7 +329,7 @@ bool rtl92se_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
|
|||
}
|
||||
|
||||
/*rx_status->qual = stats->signal; */
|
||||
rx_status->signal = stats->rssi + 10;
|
||||
rx_status->signal = stats->recvsignalpower + 10;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
@ -77,11 +77,7 @@
|
|||
#define RTL_SLOT_TIME_9 9
|
||||
#define RTL_SLOT_TIME_20 20
|
||||
|
||||
/*related with tcp/ip. */
|
||||
/*if_ehther.h*/
|
||||
#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
|
||||
#define ETH_P_IP 0x0800 /*Internet Protocol packet */
|
||||
#define ETH_P_ARP 0x0806 /*Address Resolution packet */
|
||||
/*related to tcp/ip. */
|
||||
#define SNAP_SIZE 6
|
||||
#define PROTOC_TYPE_SIZE 2
|
||||
|
||||
|
|
Loading…
Reference in a new issue