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wifi: rtw89: pci: enable CLK_REQ, ASPM, L1 and L1ss for 8852c
8852CE controls CLKREQ, ASPM L1, L1ss via wifi registers instead, so change them accordingly. Signed-off-by: Chin-Yen Lee <timlee@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220819064811.37700-5-pkshih@realtek.com
This commit is contained in:
parent
8f308ae334
commit
843059d819
2 changed files with 79 additions and 24 deletions
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@ -3293,6 +3293,7 @@ static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev)
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static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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int ret;
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if (rtw89_pci_disable_clkreq)
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@ -3303,19 +3304,33 @@ static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)
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if (ret)
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rtw89_err(rtwdev, "failed to set CLKREQ Delay\n");
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_CLK);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_CLK);
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if (ret)
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rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
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enable ? "set" : "unset", ret);
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if (chip_id == RTL8852A) {
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev,
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RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_CLK);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev,
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RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_CLK);
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if (ret)
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rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
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enable ? "set" : "unset", ret);
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} else if (chip_id == RTL8852C) {
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rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL,
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B_AX_CLK_REQ_SEL_OPT | B_AX_CLK_REQ_SEL);
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if (enable)
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rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL,
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B_AX_CLK_REQ_N);
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else
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rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL,
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B_AX_CLK_REQ_N);
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}
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}
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static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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u8 value = 0;
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int ret;
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@ -3334,12 +3349,23 @@ static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)
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if (ret)
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rtw89_err(rtwdev, "failed to read ASPM Delay\n");
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_L1);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_L1);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev,
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RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_L1);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev,
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RTW89_PCIE_L1_CTRL,
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RTW89_PCIE_BIT_L1);
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} else if (chip_id == RTL8852C) {
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if (enable)
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rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,
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B_AX_ASPM_CTRL_L1);
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else
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rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1,
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B_AX_ASPM_CTRL_L1);
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}
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if (ret)
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rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d",
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enable ? "set" : "unset", ret);
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@ -3400,17 +3426,34 @@ static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev)
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static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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int ret;
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_TIMER_CTRL,
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RTW89_PCIE_BIT_L1SUB);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_TIMER_CTRL,
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RTW89_PCIE_BIT_L1SUB);
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if (ret)
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rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
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enable ? "set" : "unset", ret);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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if (enable)
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ret = rtw89_pci_config_byte_set(rtwdev,
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RTW89_PCIE_TIMER_CTRL,
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RTW89_PCIE_BIT_L1SUB);
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else
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ret = rtw89_pci_config_byte_clr(rtwdev,
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RTW89_PCIE_TIMER_CTRL,
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RTW89_PCIE_BIT_L1SUB);
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if (ret)
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rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
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enable ? "set" : "unset", ret);
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} else if (chip_id == RTL8852C) {
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ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1,
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RTW89_PCIE_BIT_ASPM_L11 |
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RTW89_PCIE_BIT_PCI_L11);
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if (ret)
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rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret);
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if (enable)
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rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1,
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B_AX_L1SUB_DISABLE);
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else
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rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,
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B_AX_L1SUB_DISABLE);
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}
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}
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static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev)
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@ -62,9 +62,16 @@
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#define B_AX_REQ_ENTR_L1 BIT(8)
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#define B_AX_L1SUB_DISABLE BIT(0)
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#define R_AX_L1_CLK_CTRL 0x3010
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#define B_AX_CLK_REQ_N BIT(1)
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#define R_AX_PCIE_BG_CLR 0x303C
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#define B_AX_BG_CLR_ASYNC_M3 BIT(4)
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#define R_AX_PCIE_LAT_CTRL 0x3044
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#define B_AX_CLK_REQ_SEL_OPT BIT(1)
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#define B_AX_CLK_REQ_SEL BIT(0)
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#define R_AX_PCIE_IO_RCY_M1 0x3100
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#define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
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#define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
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@ -531,6 +538,11 @@
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#define RTW89_PCIE_GEN2_SPEED 0x02
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#define RTW89_PCIE_PHY_RATE 0x82
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#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
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#define RTW89_PCIE_L1SS_STS_V1 0x0168
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#define RTW89_PCIE_BIT_ASPM_L11 BIT(3)
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#define RTW89_PCIE_BIT_ASPM_L12 BIT(2)
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#define RTW89_PCIE_BIT_PCI_L11 BIT(1)
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#define RTW89_PCIE_BIT_PCI_L12 BIT(0)
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#define RTW89_PCIE_ASPM_CTRL 0x070F
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#define RTW89_L1DLY_MASK GENMASK(5, 3)
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#define RTW89_L0DLY_MASK GENMASK(2, 0)
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