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ARM: dts: stm32: add flash nor support on stm32mp157c eval board
This patch adds flash nor on qspi. Each flash is connected in quad mode and has its own chip select. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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2 changed files with 70 additions and 0 deletions
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@ -212,6 +212,51 @@ pins {
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};
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};
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qspi_clk_pins_a: qspi-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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qspi_bk1_pins_a: qspi-bk1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
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<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
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<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
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<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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qspi_bk2_pins_a: qspi-bk2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
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<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
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<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
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<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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uart4_pins_a: uart4@0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
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@ -42,6 +42,31 @@ &i2c5 {
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status = "okay";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
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reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: mx66l51235l@0 {
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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flash1: mx66l51235l@1 {
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reg = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&timers2 {
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status = "disabled";
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pwm {
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