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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/nouveau/nvif: split out ctxdma interface definitions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
75445a4d64
commit
845f27253c
12 changed files with 79 additions and 75 deletions
66
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
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66
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
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@ -0,0 +1,66 @@
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#ifndef __NVIF_CL0002_H__
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#define __NVIF_CL0002_H__
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struct nv_dma_v0 {
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__u8 version;
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#define NV_DMA_V0_TARGET_VM 0x00
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#define NV_DMA_V0_TARGET_VRAM 0x01
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#define NV_DMA_V0_TARGET_PCI 0x02
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#define NV_DMA_V0_TARGET_PCI_US 0x03
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#define NV_DMA_V0_TARGET_AGP 0x04
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__u8 target;
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#define NV_DMA_V0_ACCESS_VM 0x00
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#define NV_DMA_V0_ACCESS_RD 0x01
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#define NV_DMA_V0_ACCESS_WR 0x02
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#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
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__u8 access;
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__u8 pad03[5];
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__u64 start;
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__u64 limit;
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/* ... chipset-specific class data */
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};
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struct nv50_dma_v0 {
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__u8 version;
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#define NV50_DMA_V0_PRIV_VM 0x00
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#define NV50_DMA_V0_PRIV_US 0x01
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#define NV50_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define NV50_DMA_V0_PART_VM 0x00
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#define NV50_DMA_V0_PART_256 0x01
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#define NV50_DMA_V0_PART_1KB 0x02
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__u8 part;
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#define NV50_DMA_V0_COMP_NONE 0x00
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#define NV50_DMA_V0_COMP_1 0x01
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#define NV50_DMA_V0_COMP_2 0x02
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#define NV50_DMA_V0_COMP_VM 0x03
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__u8 comp;
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#define NV50_DMA_V0_KIND_PITCH 0x00
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#define NV50_DMA_V0_KIND_VM 0x7f
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__u8 kind;
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__u8 pad05[3];
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};
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struct gf100_dma_v0 {
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__u8 version;
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#define GF100_DMA_V0_PRIV_VM 0x00
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#define GF100_DMA_V0_PRIV_US 0x01
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#define GF100_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define GF100_DMA_V0_KIND_PITCH 0x00
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#define GF100_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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struct gf119_dma_v0 {
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__u8 version;
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#define GF119_DMA_V0_PAGE_LP 0x00
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#define GF119_DMA_V0_PAGE_SP 0x01
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__u8 page;
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#define GF119_DMA_V0_KIND_PITCH 0x00
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#define GF119_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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#endif
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@ -13,9 +13,9 @@
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_DEVICE 0x00000080
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#define NV_DMA_FROM_MEMORY 0x00000002
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#define NV_DMA_TO_MEMORY 0x00000003
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#define NV_DMA_IN_MEMORY 0x0000003d
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#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
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#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
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#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
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#define FERMI_TWOD_A 0x0000902d
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@ -198,72 +198,4 @@ struct nv_device_time_v0 {
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__u8 pad01[7];
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__u64 time;
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};
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/*******************************************************************************
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* context dma
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******************************************************************************/
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struct nv_dma_v0 {
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__u8 version;
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#define NV_DMA_V0_TARGET_VM 0x00
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#define NV_DMA_V0_TARGET_VRAM 0x01
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#define NV_DMA_V0_TARGET_PCI 0x02
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#define NV_DMA_V0_TARGET_PCI_US 0x03
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#define NV_DMA_V0_TARGET_AGP 0x04
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__u8 target;
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#define NV_DMA_V0_ACCESS_VM 0x00
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#define NV_DMA_V0_ACCESS_RD 0x01
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#define NV_DMA_V0_ACCESS_WR 0x02
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#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
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__u8 access;
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__u8 pad03[5];
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__u64 start;
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__u64 limit;
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/* ... chipset-specific class data */
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};
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struct nv50_dma_v0 {
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__u8 version;
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#define NV50_DMA_V0_PRIV_VM 0x00
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#define NV50_DMA_V0_PRIV_US 0x01
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#define NV50_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define NV50_DMA_V0_PART_VM 0x00
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#define NV50_DMA_V0_PART_256 0x01
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#define NV50_DMA_V0_PART_1KB 0x02
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__u8 part;
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#define NV50_DMA_V0_COMP_NONE 0x00
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#define NV50_DMA_V0_COMP_1 0x01
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#define NV50_DMA_V0_COMP_2 0x02
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#define NV50_DMA_V0_COMP_VM 0x03
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__u8 comp;
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#define NV50_DMA_V0_KIND_PITCH 0x00
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#define NV50_DMA_V0_KIND_VM 0x7f
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__u8 kind;
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__u8 pad05[3];
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};
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struct gf100_dma_v0 {
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__u8 version;
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#define GF100_DMA_V0_PRIV_VM 0x00
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#define GF100_DMA_V0_PRIV_US 0x01
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#define GF100_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define GF100_DMA_V0_KIND_PITCH 0x00
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#define GF100_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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struct gf119_dma_v0 {
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__u8 version;
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#define GF119_DMA_V0_PAGE_LP 0x00
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#define GF119_DMA_V0_PAGE_SP 0x01
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__u8 page;
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#define GF119_DMA_V0_KIND_PITCH 0x00
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#define GF119_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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#endif
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@ -25,6 +25,7 @@
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#include <nvif/driver.h>
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#include <nvif/ioctl.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/cla06f.h>
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#include <nvif/unpack.h>
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@ -24,6 +24,7 @@
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#include <nvif/os.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/cl006b.h>
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#include <nvif/cl506f.h>
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#include <nvif/cl906f.h>
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@ -37,6 +37,7 @@
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#include <core/pci.h>
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#include <core/tegra.h>
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#include <nvif/cl0002.h>
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#include <nvif/cla06f.h>
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#include <nvif/if0004.h>
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@ -24,6 +24,7 @@
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#include <nvif/os.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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@ -31,6 +31,7 @@
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#include <drm/drm_fb_helper.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/cl5070.h>
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#include <nvif/cl507a.h>
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#include <nvif/cl507b.h>
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@ -24,6 +24,7 @@
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#include <nvif/os.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/unpack.h>
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static int
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@ -28,7 +28,7 @@
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/unpack.h>
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struct gf100_dmaobj {
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/unpack.h>
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struct gf119_dmaobj {
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/unpack.h>
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struct nv50_dmaobj {
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