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PCI: Disable D3cold on Asus B1400 PCI-NVMe bridge
[ Upstream commit cdea98bf1f
]
The Asus B1400 with original shipped firmware versions and VMD disabled
cannot resume from suspend: the NVMe device becomes unresponsive and
inaccessible.
This appears to be an untested D3cold transition by the vendor; Intel
socwatch shows that Windows leaves the NVMe device and parent bridge in D0
during suspend, even though these firmware versions have StorageD3Enable=1.
The NVMe device and parent PCI bridge both share the same "PXP" ACPI power
resource, which gets turned off as both devices are put into D3cold during
suspend. The _OFF() method calls DL23() which sets a L23E bit at offset
0xe2 into the PCI configuration space for this root port. This is the
specific write that the _ON() routine is unable to recover from. This
register is not documented in the public chipset datasheet.
Disallow D3cold on the PCI bridge to enable successful suspend/resume.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=215742
Link: https://lore.kernel.org/r/20240228075316.7404-1-drake@endlessos.org
Signed-off-by: Daniel Drake <drake@endlessos.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jian-Hong Pan <jhp@endlessos.org>
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 48 additions and 0 deletions
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@ -907,6 +907,54 @@ static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
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/*
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* Disable D3cold on Asus B1400 PCI-NVMe bridge
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*
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* On this platform with VMD off, the NVMe device cannot successfully power
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* back on from D3cold. This appears to be an untested transition by the
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* vendor: Windows leaves the NVMe and parent bridge in D0 during suspend.
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*
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* We disable D3cold on the parent bridge for simplicity, and the fact that
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* both parent bridge and NVMe device share the same power resource.
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*
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* This is only needed on BIOS versions before 308; the newer versions flip
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* StorageD3Enable from 1 to 0.
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*/
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static const struct dmi_system_id asus_nvme_broken_d3cold_table[] = {
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
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DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.304"),
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},
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},
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
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DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.305"),
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},
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},
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
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DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.306"),
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},
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},
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
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DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.307"),
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},
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},
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{}
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};
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static void asus_disable_nvme_d3cold(struct pci_dev *pdev)
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{
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if (dmi_check_system(asus_nvme_broken_d3cold_table) > 0)
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pci_d3cold_disable(pdev);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold);
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#ifdef CONFIG_SUSPEND
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/*
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* Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but
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