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clk: mvebu: add a little bit of documentation about data structures
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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1 changed files with 17 additions and 0 deletions
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@ -22,12 +22,24 @@
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#define CORE_CLK_DIV_ENABLE_OFFSET 24
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#define CORE_CLK_DIV_ENABLE_OFFSET 24
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#define CORE_CLK_DIV_RATIO_OFFSET 0x8
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#define CORE_CLK_DIV_RATIO_OFFSET 0x8
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/*
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* This structure describes the hardware details (bit offset and mask)
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* to configure one particular core divider clock. Those hardware
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* details may differ from one SoC to another. This structure is
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* therefore typically instantiated statically to describe the
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* hardware details.
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*/
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struct clk_corediv_desc {
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struct clk_corediv_desc {
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unsigned int mask;
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unsigned int mask;
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unsigned int offset;
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unsigned int offset;
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unsigned int fieldbit;
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unsigned int fieldbit;
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};
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};
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/*
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* This structure represents one core divider clock for the clock
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* framework, and is dynamically allocated for each core divider clock
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* existing in the current SoC.
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*/
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struct clk_corediv {
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struct clk_corediv {
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struct clk_hw hw;
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *reg;
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@ -37,6 +49,11 @@ struct clk_corediv {
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static struct clk_onecell_data clk_data;
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static struct clk_onecell_data clk_data;
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/*
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* Description of the core divider clocks available. For now, we
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* support only NAND, and it is available at the same register
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* locations regardless of the SoC.
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*/
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static const struct clk_corediv_desc mvebu_corediv_desc[] = {
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static const struct clk_corediv_desc mvebu_corediv_desc[] = {
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{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
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{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
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};
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};
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