ARM: dts: stm32: add stm32mp157c initial support
Add stm32mp157c initial support with: -Dual Cortex-A7 -Arm psci, timer, gic -Pinctrl -Uart Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Ludovic Barre
Alexandre Torgue
parent
a45011956d
commit
8471a20253
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-pinctrl";
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ranges = <0 0x50002000 0xa400>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOA";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 0 16>;
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};
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gpiob: gpio@50003000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOB";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 16 16>;
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};
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gpioc: gpio@50004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOC";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 32 16>;
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};
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gpiod: gpio@50005000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOD";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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gpioe: gpio@50006000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOE";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 64 16>;
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};
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gpiof: gpio@50007000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOF";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 80 16>;
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};
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gpiog: gpio@50008000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOG";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 96 16>;
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};
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gpioh: gpio@50009000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOH";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 112 16>;
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};
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gpioi: gpio@5000a000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x8000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOI";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 128 16>;
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};
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gpioj: gpio@5000b000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x9000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOJ";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 144 16>;
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};
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gpiok: gpio@5000c000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa000 0x400>;
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clocks = <&clk_pll3_p>;
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st,bank-name = "GPIOK";
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ngpios = <8>;
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gpio-ranges = <&pinctrl 0 160 8>;
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};
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};
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pinctrl_z: pin-controller-z {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-z-pinctrl";
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ranges = <0 0x54004000 0x400>;
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pins-are-numbered;
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status = "disabled";
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gpioz: gpio@54004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x400>;
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clocks = <&clk_pll2_p>;
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st,bank-name = "GPIOZ";
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st,bank-ioport = <11>;
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ngpios = <8>;
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gpio-ranges = <&pinctrl_z 0 400 8>;
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};
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};
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};
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};
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@ -0,0 +1,194 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_pll_per: clk-pll-per {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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clk_pclk1: clk-pclk1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <86000000>;
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};
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clk_pll3_p: clk-pll3_p {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <172000000>;
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};
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clk_pll2_p: clk-pll2_p {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <264000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000e000 0x400>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000f000 0x400>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-uart";
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reg = <0x44003000 0x400>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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usart1: serial@5c000000 {
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compatible = "st,stm32h7-uart";
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reg = <0x5c000000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
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clocks = <&clk_pclk1>;
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status = "disabled";
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};
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};
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};
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