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ARM: 7823/1: errata: workaround Cortex-A15 erratum 773022

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On Cortex-A15 CPUs up to and including r0p4, in certain rare sequences
of code, the loop buffer may deliver incorrect instructions. This
workaround disables the loop buffer to avoid the erratum.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Will Deacon 2013-08-20 17:29:55 +01:00 committed by Russell King
parent 2afd0a0524
commit 84b6504f56
2 changed files with 22 additions and 1 deletions
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9
arch/arm/Kconfig
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@ -1373,6 +1373,15 @@ config ARM_ERRATA_798181
which sends an IPI to the CPUs that are running the same ASID
as the one being invalidated.
config ARM_ERRATA_773022
bool "ARM errata: incorrect instructions may be executed from loop buffer"
depends on CPU_V7
help
This option enables the workaround for the 773022 Cortex-A15
(up to r0p4) erratum. In certain rare sequences of code, the
loop buffer may deliver incorrect instructions. This
workaround disables the loop buffer to avoid the erratum.
endmenu
source "arch/arm/common/Kconfig"

14
arch/arm/mm/proc-v7.S
View file

@ -329,7 +329,19 @@ __v7_setup:
1:
#endif
3: mov r10, #0
/* Cortex-A15 Errata */
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
teq r0, r10
bne 4f
#ifdef CONFIG_ARM_ERRATA_773022
cmp r6, #0x4 @ only present up to r0p4
mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
orrle r10, r10, #1 << 1 @ disable loop buffer
mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
#endif
4: mov r10, #0
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
dsb
#ifdef CONFIG_MMU