diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt new file mode 100644 index 000000000000..a63ccd476cda --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt @@ -0,0 +1,87 @@ +Renesas RZ/A2 combined Pin and GPIO controller + +The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller. +Pin multiplexing and GPIO configuration is performed on a per-pin basis. +Each port features up to 8 pins, each of them configurable for GPIO +function (port mode) or in alternate function mode. +Up to 8 different alternate function modes exist for each single pin. + +Pin controller node +------------------- + +Required properties: + - compatible: shall be: + - "renesas,r7s9210-pinctrl": for RZ/A2M + - reg + Address base and length of the memory area where the pin controller + hardware is mapped to. + - gpio-controller + This pin controller also controls pins as GPIO + - #gpio-cells + Must be 2 + - gpio-ranges + Expresses the total number of GPIO ports/pins in this SoC + +Example: Pin controller node for RZ/A2M SoC (r7s9210) + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + +Sub-nodes +--------- + +The child nodes of the pin controller designate pins to be used for +specific peripheral functions or as GPIO. + +- Pin multiplexing sub-nodes: + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + The values for the pinmux properties are a combination of port name, pin + number and the desired function index. Use the RZA2_PINMUX macro located + in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these. + For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h + to express the desired port pin. + + Required properties: + - pinmux: + integer array representing pin number and pin multiplexing configuration. + When a pin has to be configured in alternate function mode, use this + property to identify the pin by its global index, and provide its + alternate function configuration number along with it. + When multiple pins are required to be configured as part of the same + alternate function they shall be specified as members of the same + argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function identifier + are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 8 + PIN) | MUX_FUNC << 16) + + Example: Board specific pins configuration + + &pinctrl { + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; + }; + + Example: Assigning a GPIO: + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led0 { + /* P6_0 */ + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f4855974f325..35d56b05dfa9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11749,11 +11749,11 @@ F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt F: drivers/pinctrl/qcom/ PIN CONTROLLER - RENESAS -M: Laurent Pinchart M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc S: Maintained +F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ PIN CONTROLLER - SAMSUNG diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4d8c00eac742..4c6e83ef716d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -195,6 +195,17 @@ config PINCTRL_RZA1 help This selects pinctrl driver for Renesas RZ/A1 platforms. +config PINCTRL_RZA2 + bool "Renesas RZ/A2 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S9210 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. + config PINCTRL_RZN1 bool "Renesas RZ/N1 pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 18a13c1e2c21..712184b74a5c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o +obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c new file mode 100644 index 000000000000..5b951c7422cc --- /dev/null +++ b/drivers/pinctrl/pinctrl-rza2.c @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC + * + * Copyright (C) 2018 Chris Brandt + */ + +/* + * This pin controller/gpio combined driver supports Renesas devices of RZ/A2 + * family. + */ + +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" + +#define DRIVER_NAME "pinctrl-rza2" + +#define RZA2_PINS_PER_PORT 8 +#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT) +#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT) + +/* + * Use 16 lower bits [15:0] for pin identifier + * Use 16 higher bits [31:16] for pin mux function + */ +#define MUX_PIN_ID_MASK GENMASK(15, 0) +#define MUX_FUNC_MASK GENMASK(31, 16) +#define MUX_FUNC_OFFS 16 +#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) + +static const char port_names[] = "0123456789ABCDEFGHJKLM"; + +struct rza2_pinctrl_priv { + struct device *dev; + void __iomem *base; + + struct pinctrl_pin_desc *pins; + struct pinctrl_desc desc; + struct pinctrl_dev *pctl; + struct pinctrl_gpio_range gpio_range; + int npins; +}; + +#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */ +#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */ +#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */ +#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */ +#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */ +#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */ + +#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */ +#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */ +#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */ +#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */ +#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */ + +#define RZA2_PDR_INPUT 0x02 +#define RZA2_PDR_OUTPUT 0x03 +#define RZA2_PDR_MASK 0x03 + +#define PWPR_B0WI BIT(7) /* Bit Write Disable */ +#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */ +#define PFS_ISEL BIT(6) /* Interrupt Select */ + +static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin, + u8 func) +{ + u16 mask16; + u16 reg16; + u8 reg8; + + /* Set pin to 'Non-use (Hi-z input protection)' */ + reg16 = readw(pfc_base + RZA2_PDR(port)); + mask16 = RZA2_PDR_MASK << (pin * 2); + reg16 &= ~mask16; + writew(reg16, pfc_base + RZA2_PDR(port)); + + /* Temporarily switch to GPIO */ + reg8 = readb(pfc_base + RZA2_PMR(port)); + reg8 &= ~BIT(pin); + writeb(reg8, pfc_base + RZA2_PMR(port)); + + /* PFS Register Write Protect : OFF */ + writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */ + writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */ + + /* Set Pin function (interrupt disabled, ISEL=0) */ + writeb(func, pfc_base + RZA2_PFS(port, pin)); + + /* PFS Register Write Protect : ON */ + writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */ + writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */ + + /* Port Mode : Peripheral module pin functions */ + reg8 = readb(pfc_base + RZA2_PMR(port)); + reg8 |= BIT(pin); + writeb(reg8, pfc_base + RZA2_PMR(port)); +} + +static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset, + u8 dir) +{ + u8 port = RZA2_PIN_ID_TO_PORT(offset); + u8 pin = RZA2_PIN_ID_TO_PIN(offset); + u16 mask16; + u16 reg16; + + reg16 = readw(pfc_base + RZA2_PDR(port)); + mask16 = RZA2_PDR_MASK << (pin * 2); + reg16 &= ~mask16; + + if (dir == GPIOF_DIR_IN) + reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */ + else + reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */ + + writew(reg16, pfc_base + RZA2_PDR(port)); +} + +static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); + u8 port = RZA2_PIN_ID_TO_PORT(offset); + u8 pin = RZA2_PIN_ID_TO_PIN(offset); + u16 reg16; + + reg16 = readw(priv->base + RZA2_PDR(port)); + reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK; + + if (reg16 == RZA2_PDR_OUTPUT) + return GPIOF_DIR_OUT; + + if (reg16 == RZA2_PDR_INPUT) + return GPIOF_DIR_IN; + + /* + * This GPIO controller has a default Hi-Z state that is not input or + * output, so force the pin to input now. + */ + rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN); + + return GPIOF_DIR_IN; +} + +static int rza2_chip_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); + + rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN); + + return 0; +} + +static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); + u8 port = RZA2_PIN_ID_TO_PORT(offset); + u8 pin = RZA2_PIN_ID_TO_PIN(offset); + + return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); +} + +static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); + u8 port = RZA2_PIN_ID_TO_PORT(offset); + u8 pin = RZA2_PIN_ID_TO_PIN(offset); + u8 new_value; + + new_value = readb(priv->base + RZA2_PODR(port)); + + if (value) + new_value |= BIT(pin); + else + new_value &= ~BIT(pin); + + writeb(new_value, priv->base + RZA2_PODR(port)); +} + +static int rza2_chip_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); + + rza2_chip_set(chip, offset, val); + rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT); + + return 0; +} + +static const char * const rza2_gpio_names[] = { + "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", + "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", + "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", + "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", + "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", + "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", + "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", + "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", + "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", + "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", + "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7", + "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7", + "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7", + "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7", + "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7", + "PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7", + "PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7", + "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7", + /* port I does not exist */ + "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7", + "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7", + "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7", + "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7", +}; + +static struct gpio_chip chip = { + .names = rza2_gpio_names, + .base = -1, + .get_direction = rza2_chip_get_direction, + .direction_input = rza2_chip_direction_input, + .direction_output = rza2_chip_direction_output, + .get = rza2_chip_get, + .set = rza2_chip_set, +}; + +static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) +{ + struct device_node *np = priv->dev->of_node; + struct of_phandle_args of_args; + int ret; + + chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); + chip.of_node = np; + chip.parent = priv->dev; + chip.ngpio = priv->npins; + + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, + &of_args); + if (ret) { + dev_err(priv->dev, "Unable to parse gpio-ranges\n"); + return ret; + } + + if ((of_args.args[0] != 0) || + (of_args.args[1] != 0) || + (of_args.args[2] != priv->npins)) { + dev_err(priv->dev, "gpio-ranges does not match selected SOC\n"); + return -EINVAL; + } + priv->gpio_range.id = 0; + priv->gpio_range.pin_base = priv->gpio_range.base = 0; + priv->gpio_range.npins = priv->npins; + priv->gpio_range.name = chip.label; + priv->gpio_range.gc = &chip; + + /* Register our gpio chip with gpiolib */ + ret = devm_gpiochip_add_data(priv->dev, &chip, priv); + if (ret) + return ret; + + /* Register pin range with pinctrl core */ + pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range); + + dev_dbg(priv->dev, "Registered gpio controller\n"); + + return 0; +} + +static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv) +{ + struct pinctrl_pin_desc *pins; + unsigned int i; + int ret; + + pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + priv->pins = pins; + priv->desc.pins = pins; + priv->desc.npins = priv->npins; + + for (i = 0; i < priv->npins; i++) { + pins[i].number = i; + pins[i].name = rza2_gpio_names[i]; + } + + ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, + &priv->pctl); + if (ret) { + dev_err(priv->dev, "pinctrl registration failed\n"); + return ret; + } + + ret = pinctrl_enable(priv->pctl); + if (ret) { + dev_err(priv->dev, "pinctrl enable failed\n"); + return ret; + } + + ret = rza2_gpio_register(priv); + if (ret) { + dev_err(priv->dev, "GPIO registration failed\n"); + return ret; + } + + return 0; +} + +/* + * For each DT node, create a single pin mapping. That pin mapping will only + * contain a single group of pins, and that group of pins will only have a + * single function that can be selected. + */ +static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int *pins, *psel_val; + int i, ret, npins, gsel, fsel; + struct property *of_pins; + const char **pin_fn; + + /* Find out how many pins to map */ + of_pins = of_find_property(np, "pinmux", NULL); + if (!of_pins) { + dev_info(priv->dev, "Missing pinmux property\n"); + return -ENOENT; + } + npins = of_pins->length / sizeof(u32); + + pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL); + psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val), + GFP_KERNEL); + pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL); + if (!pins || !psel_val || !pin_fn) + return -ENOMEM; + + /* Collect pin locations and mux settings from DT properties */ + for (i = 0; i < npins; ++i) { + u32 value; + + ret = of_property_read_u32_index(np, "pinmux", i, &value); + if (ret) + return ret; + pins[i] = value & MUX_PIN_ID_MASK; + psel_val[i] = MUX_FUNC(value); + } + + /* Register a single pin group listing all the pins we read from DT */ + gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL); + if (gsel < 0) + return gsel; + + /* + * Register a single group function where the 'data' is an array PSEL + * register values read from DT. + */ + pin_fn[0] = np->name; + fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, + psel_val); + if (fsel < 0) { + ret = fsel; + goto remove_group; + } + + dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins); + + /* Create map where to retrieve function and mux settings from */ + *num_maps = 0; + *map = kzalloc(sizeof(**map), GFP_KERNEL); + if (!*map) { + ret = -ENOMEM; + goto remove_function; + } + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + *num_maps = 1; + + return 0; + +remove_function: + pinmux_generic_remove_function(pctldev, fsel); + +remove_group: + pinctrl_generic_remove_group(pctldev, gsel); + + dev_err(priv->dev, "Unable to parse DT node %s\n", np->name); + + return ret; +} + +static void rza2_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops rza2_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = rza2_dt_node_to_map, + .dt_free_map = rza2_dt_free_map, +}; + +static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + unsigned int i, *psel_val; + struct group_desc *grp; + + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, selector); + if (!func) + return -EINVAL; + + psel_val = func->data; + + for (i = 0; i < grp->num_pins; ++i) { + dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n", + port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])], + RZA2_PIN_ID_TO_PIN(grp->pins[i]), + psel_val[i]); + rza2_set_pin_function( + priv->base, + RZA2_PIN_ID_TO_PORT(grp->pins[i]), + RZA2_PIN_ID_TO_PIN(grp->pins[i]), + psel_val[i]); + } + + return 0; +} + +static const struct pinmux_ops rza2_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = rza2_set_mux, + .strict = true, +}; + +static int rza2_pinctrl_probe(struct platform_device *pdev) +{ + struct rza2_pinctrl_priv *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + platform_set_drvdata(pdev, priv); + + priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * + RZA2_PINS_PER_PORT; + + priv->desc.name = DRIVER_NAME; + priv->desc.pctlops = &rza2_pinctrl_ops; + priv->desc.pmxops = &rza2_pinmux_ops; + priv->desc.owner = THIS_MODULE; + + ret = rza2_pinctrl_register(priv); + if (ret) + return ret; + + dev_info(&pdev->dev, "Registered ports P0 - P%c\n", + port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]); + + return 0; +} + +static const struct of_device_id rza2_pinctrl_of_match[] = { + { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, }, + { /* sentinel */ } +}; + +static struct platform_driver rza2_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = rza2_pinctrl_of_match, + }, + .probe = rza2_pinctrl_probe, +}; + +static int __init rza2_pinctrl_init(void) +{ + return platform_driver_register(&rza2_pinctrl_driver); +} +core_initcall(rza2_pinctrl_init); + +MODULE_AUTHOR("Chris Brandt "); +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 3d36e5f4ca7b..4359aeb35dbd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -10,14 +10,45 @@ #include "sh_pfc.h" #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_23(0, fn, sfx), \ + PORT_GP_4(0, fn, sfx), \ + PORT_GP_1(0, 4, fn, sfx), \ + PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(0, 11, fn, sfx), \ + PORT_GP_1(0, 12, fn, sfx), \ + PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_23(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ PORT_GP_17(3, fn, sfx), \ PORT_GP_1(3, 27, fn, sfx), \ PORT_GP_1(3, 28, fn, sfx), \ PORT_GP_1(3, 29, fn, sfx), \ - PORT_GP_26(4, fn, sfx), \ + PORT_GP_14(4, fn, sfx), \ + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(4, 20, fn, sfx), \ + PORT_GP_1(4, 21, fn, sfx), \ + PORT_GP_1(4, 22, fn, sfx), \ + PORT_GP_1(4, 23, fn, sfx), \ + PORT_GP_1(4, 24, fn, sfx), \ + PORT_GP_1(4, 25, fn, sfx), \ PORT_GP_32(5, fn, sfx) enum { @@ -1284,6 +1315,229 @@ static const unsigned int du0_disp_pins[] = { static const unsigned int du0_disp_mux[] = { DU0_DISP_MARK }; +static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), +}; +static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, +}; +static const unsigned int du1_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), +}; +static const unsigned int du1_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, +}; +static const unsigned int du1_clk0_out_pins[] = { + /* DOTCLKOUT0 */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int du1_clk0_out_mux[] = { + DU1_DOTCLKOUT0_MARK +}; +static const unsigned int du1_clk1_out_pins[] = { + /* DOTCLKOUT1 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int du1_clk1_out_mux[] = { + DU1_DOTCLKOUT1_MARK +}; +static const unsigned int du1_clk_in_pins[] = { + /* DOTCLKIN */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK +}; +static const unsigned int du1_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4), +}; +static const unsigned int du1_sync_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK +}; +static const unsigned int du1_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du1_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK +}; +static const unsigned int du1_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(5, 6), +}; +static const unsigned int du1_disp_mux[] = { + DU1_DISP_MARK +}; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int i2c0_a_mux[] = { + SCL0_A_MARK, SDA0_A_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), +}; +static const unsigned int i2c0_b_mux[] = { + SCL0_B_MARK, SDA0_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c0_c_mux[] = { + SCL0_C_MARK, SDA0_C_MARK, +}; +static const unsigned int i2c0_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int i2c0_d_mux[] = { + SCL0_D_MARK, SDA0_D_MARK, +}; +static const unsigned int i2c0_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c0_e_mux[] = { + SCL0_E_MARK, SDA0_E_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int i2c1_a_mux[] = { + SCL1_A_MARK, SDA1_A_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int i2c1_e_mux[] = { + SCL1_E_MARK, SDA1_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), +}; +static const unsigned int i2c2_a_mux[] = { + SCL2_A_MARK, SDA2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int i2c3_a_mux[] = { + SCL3_A_MARK, SDA3_A_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int i2c3_c_mux[] = { + SCL3_C_MARK, SDA3_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int i2c3_d_mux[] = { + SCL3_D_MARK, SDA3_D_MARK, +}; +static const unsigned int i2c3_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), +}; +static const unsigned int i2c3_e_mux[] = { + SCL3_E_MARK, SDA3_E_MARK, +}; /* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_a_pins[] = { /* SCL, SDA */ @@ -1381,6 +1635,29 @@ static const unsigned int qspi0_data4_mux[] = { QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1619,6 +1896,81 @@ static const unsigned int scif_clk_b_pins[] = { static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int sdhi1_data1_mux[] = { + MMC0_D0_SDHI1_D0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), +}; +static const unsigned int sdhi1_data4_mux[] = { + MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, + MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; /* - SDHI2 ------------------------------------------------------------------ */ static const unsigned int sdhi2_data1_pins[] = { /* D0 */ @@ -1674,6 +2026,146 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(5, 30), /* HSYNC */ + RCAR_GP_PIN(5, 31), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(5, 29), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(5, 28), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(5, 18), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data12 = { + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + }, +}; +static const union vin_data vin1_data_mux = { + .data12 = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, + }, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(3, 11), /* HSYNC */ + RCAR_GP_PIN(3, 12), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(3, 10), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(3, 9), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -1698,6 +2190,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_oddf), SH_PFC_PIN_GROUP(du0_cde), SH_PFC_PIN_GROUP(du0_disp), + SH_PFC_PIN_GROUP(du1_rgb666), + SH_PFC_PIN_GROUP(du1_rgb888), + SH_PFC_PIN_GROUP(du1_clk0_out), + SH_PFC_PIN_GROUP(du1_clk1_out), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_sync), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(du1_disp), + SH_PFC_PIN_GROUP(i2c0_a), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c0_d), + SH_PFC_PIN_GROUP(i2c0_e), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c3_e), SH_PFC_PIN_GROUP(i2c4_a), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), @@ -1710,6 +2230,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP(qspi0_data2), SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -1743,6 +2266,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_f), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), @@ -1750,6 +2283,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), }; static const char * const avb_groups[] = { @@ -1780,6 +2331,49 @@ static const char * const du0_groups[] = { "du0_disp", }; +static const char * const du1_groups[] = { + "du1_rgb666", + "du1_rgb888", + "du1_clk0_out", + "du1_clk1_out", + "du1_clk_in", + "du1_sync", + "du1_oddf", + "du1_cde", + "du1_disp", +}; + +static const char * const i2c0_groups[] = { + "i2c0_a", + "i2c0_b", + "i2c0_c", + "i2c0_d", + "i2c0_e", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", + "i2c3_d", + "i2c3_e", +}; + static const char * const i2c4_groups[] = { "i2c4_a", "i2c4_b", @@ -1801,6 +2395,12 @@ static const char * const qspi0_groups[] = { "qspi0_data4", }; +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_data_b", @@ -1855,6 +2455,22 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + static const char * const sdhi2_groups[] = { "sdhi2_data1", "sdhi2_data4", @@ -1871,12 +2487,42 @@ static const char * const usb1_groups[] = { "usb1", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -1884,9 +2530,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -2729,9 +3379,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = 0xe60600b0; + + if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10)) + bit = 0; + + if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22)) + bit = 2; + + if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19)) + bit = 1; + + return bit; +} + +static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { + .pin_to_pocctrl = r8a77470_pin_to_pocctrl, +}; + #ifdef CONFIG_PINCTRL_PFC_R8A77470 const struct sh_pfc_soc_info r8a77470_pinmux_info = { .name = "r8a77470_pfc", + .ops = &r8a77470_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index bf0681b38181..a623459b234e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1474,7 +1474,7 @@ static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; /* - VIN2 ------------------------------------------------------------------- */ -static const union vin_data vin2_data_pins = { +static const union vin_data16 vin2_data_pins = { .data16 = { RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), @@ -1486,7 +1486,7 @@ static const union vin_data vin2_data_pins = { RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }, }; -static const union vin_data vin2_data_mux = { +static const union vin_data16 vin2_data_mux = { .data16 = { VI2_D0_C0_MARK, VI2_D1_C1_MARK, VI2_D2_C2_MARK, VI2_D3_C3_MARK, @@ -1524,7 +1524,7 @@ static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; /* - VIN3 ------------------------------------------------------------------- */ -static const union vin_data vin3_data_pins = { +static const union vin_data16 vin3_data_pins = { .data16 = { RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), @@ -1536,7 +1536,7 @@ static const union vin_data vin3_data_pins = { RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), }, }; -static const union vin_data vin3_data_mux = { +static const union vin_data16 vin3_data_mux = { .data16 = { VI3_D0_C0_MARK, VI3_D1_C1_MARK, VI3_D2_C2_MARK, VI3_D3_C3_MARK, @@ -1574,7 +1574,7 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; /* - VIN4 ------------------------------------------------------------------- */ -static const union vin_data vin4_data_pins = { +static const union vin_data12 vin4_data_pins = { .data12 = { RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), @@ -1584,7 +1584,7 @@ static const union vin_data vin4_data_pins = { RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), }, }; -static const union vin_data vin4_data_mux = { +static const union vin_data12 vin4_data_mux = { .data12 = { VI4_D0_C0_MARK, VI4_D1_C1_MARK, VI4_D2_C2_MARK, VI4_D3_C3_MARK, @@ -1620,7 +1620,7 @@ static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data vin5_data_pins = { +static const union vin_data12 vin5_data_pins = { .data12 = { RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), @@ -1630,7 +1630,7 @@ static const union vin_data vin5_data_pins = { RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), }, }; -static const union vin_data vin5_data_mux = { +static const union vin_data12 vin5_data_mux = { .data12 = { VI5_D0_C0_MARK, VI5_D1_C1_MARK, VI5_D2_C2_MARK, VI5_D3_C3_MARK, @@ -1744,10 +1744,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { VIN_DATA_PIN_GROUP(vin1_data, 12), VIN_DATA_PIN_GROUP(vin1_data, 10), VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data_b, 24), - VIN_DATA_PIN_GROUP(vin1_data_b, 20), + VIN_DATA_PIN_GROUP(vin1_data, 24, _b), + VIN_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data_b, 16), + VIN_DATA_PIN_GROUP(vin1_data, 16, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 6d1e5fdc03f8..b96a3cc79084 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -3704,7 +3704,7 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { +static const union vin_data12 vin1_data_pins = { .data12 = { RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), @@ -3714,7 +3714,7 @@ static const union vin_data vin1_data_pins = { RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), }, }; -static const union vin_data vin1_data_mux = { +static const union vin_data12 vin1_data_mux = { .data12 = { VI1_DATA0_MARK, VI1_DATA1_MARK, VI1_DATA2_MARK, VI1_DATA3_MARK, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 8c7de44615d1..287cfbb7e992 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -537,6 +537,9 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -562,6 +565,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -574,9 +578,6 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(HDMI0_CEC), PINMUX_SINGLE(HDMI1_CEC), - PINMUX_SINGLE(I2C_SEL_0_1), - PINMUX_SINGLE(I2C_SEL_3_1), - PINMUX_SINGLE(I2C_SEL_5_1), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -608,13 +609,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -664,16 +667,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_GPSR(IP1_23_20, A21), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_GPSR(IP1_27_24, A20), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1067,11 +1072,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP10_27_24, SCK0), PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2266,6 +2273,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2294,6 +2310,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -3936,10 +3971,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4309,6 +4347,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4319,6 +4361,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -4651,8 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 0af737d11403..01105bb83598 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -550,6 +550,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -575,6 +578,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -588,9 +592,6 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(HDMI0_CEC), PINMUX_SINGLE(HDMI1_CEC), - PINMUX_SINGLE(I2C_SEL_0_1), - PINMUX_SINGLE(I2C_SEL_3_1), - PINMUX_SINGLE(I2C_SEL_5_1), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -614,14 +615,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), - PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -674,14 +677,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1113,11 +1118,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2348,6 +2355,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2376,6 +2392,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -4258,10 +4293,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4474,20 +4512,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data_a, 8), - VIN_DATA_PIN_GROUP(vin4_data_a, 10), - VIN_DATA_PIN_GROUP(vin4_data_a, 12), - VIN_DATA_PIN_GROUP(vin4_data_a, 16), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data_a, 20), - VIN_DATA_PIN_GROUP(vin4_data_a, 24), - VIN_DATA_PIN_GROUP(vin4_data_b, 8), - VIN_DATA_PIN_GROUP(vin4_data_b, 10), - VIN_DATA_PIN_GROUP(vin4_data_b, 12), - VIN_DATA_PIN_GROUP(vin4_data_b, 16), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data_b, 20), - VIN_DATA_PIN_GROUP(vin4_data_b, 24), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4662,6 +4700,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4672,6 +4714,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5032,8 +5082,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 3a6d21d87107..4b98ad8d93d9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -556,6 +556,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -581,6 +584,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -617,13 +621,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -675,14 +681,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1115,13 +1123,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2347,6 +2357,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2375,6 +2394,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -4124,7 +4162,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[307]; + struct sh_pfc_pin_group common[310]; struct sh_pfc_pin_group automotive[33]; } pinmux_groups = { .common = { @@ -4197,10 +4235,13 @@ static const struct { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4409,20 +4450,20 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data_a, 8), - VIN_DATA_PIN_GROUP(vin4_data_a, 10), - VIN_DATA_PIN_GROUP(vin4_data_a, 12), - VIN_DATA_PIN_GROUP(vin4_data_a, 16), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data_a, 20), - VIN_DATA_PIN_GROUP(vin4_data_a, 24), - VIN_DATA_PIN_GROUP(vin4_data_b, 8), - VIN_DATA_PIN_GROUP(vin4_data_b, 10), - VIN_DATA_PIN_GROUP(vin4_data_b, 12), - VIN_DATA_PIN_GROUP(vin4_data_b, 16), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data_b, 20), - VIN_DATA_PIN_GROUP(vin4_data_b, 24), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4629,6 +4670,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4639,6 +4684,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -4967,7 +5020,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[45]; + struct sh_pfc_function common[48]; struct sh_pfc_function automotive[6]; } pinmux_functions = { .common = { @@ -4983,8 +5036,11 @@ static const struct { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index dfdd982984d4..a7c4882de09e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -1784,6 +1784,72 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; + +static const unsigned int can0_data_a_mux[] = { + CAN0_TX_A_MARK, CAN0_RX_A_MARK, +}; + +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; + +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; + +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 25), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; + +static const unsigned int canfd0_data_a_mux[] = { + CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +}; + +static const unsigned int canfd0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int canfd0_data_b_mux[] = { + CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +}; + +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; + +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3725,6 +3791,216 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_a_pins[] = { + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const union vin_data vin4_data_a_pins = { + .data24 = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; + +static const union vin_data vin4_data_a_mux = { + .data24 = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; + +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const union vin_data vin4_data_b_pins = { + .data24 = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + }, +}; + +static const union vin_data vin4_data_b_mux = { + .data24 = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; + +static const unsigned int vin4_sync_pins[] = { + /* VSYNC_N, HSYNC_N */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; + +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; + +static const unsigned int vin4_field_pins[] = { + RCAR_GP_PIN(1, 16), +}; + +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; + +static const unsigned int vin4_clkenb_pins[] = { + RCAR_GP_PIN(1, 19), +}; + +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; + +static const unsigned int vin4_clk_pins[] = { + RCAR_GP_PIN(1, 27), +}; + +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const union vin_data16 vin5_data_pins = { + .data16 = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + }, +}; + +static const union vin_data16 vin5_data_mux = { + .data16 = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, + }, +}; + +static const unsigned int vin5_sync_pins[] = { + /* VSYNC_N, HSYNC_N */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), +}; + +static const unsigned int vin5_sync_mux[] = { + VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, +}; + +static const unsigned int vin5_field_pins[] = { + RCAR_GP_PIN(1, 11), +}; + +static const unsigned int vin5_field_mux[] = { + VI5_FIELD_MARK, +}; + +static const unsigned int vin5_clkenb_pins[] = { + RCAR_GP_PIN(1, 20), +}; + +static const unsigned int vin5_clkenb_mux[] = { + VI5_CLKENB_MARK, +}; + +static const unsigned int vin5_clk_pins[] = { + RCAR_GP_PIN(1, 21), +}; + +static const unsigned int vin5_clk_mux[] = { + VI5_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -3754,6 +4030,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4000,6 +4283,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 8), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const audio_clk_groups[] = { @@ -4036,6 +4345,28 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data_a", + "canfd0_data_b", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4392,9 +4723,46 @@ static const char * const usb30_groups[] = { "usb30", }; +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data18_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data18_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8", + "vin5_data10", + "vin5_data12", + "vin5_data16", + "vin5_sync", + "vin5_field", + "vin5_clkenb", + "vin5_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4432,6 +4800,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c index 44f9eefc86b5..443074d39f29 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -1382,6 +1382,56 @@ static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -1756,6 +1806,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data), @@ -1950,6 +2006,18 @@ static const char * const pwm4_groups[] = { "pwm4_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif_clk_groups[] = { "scif_clk_a", "scif_clk_b", @@ -2033,6 +2101,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c index 3f6967331f64..aa1d50b398c5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -1660,6 +1660,56 @@ static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX0, TX0 */ @@ -2092,6 +2142,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2316,6 +2372,18 @@ static const char * const pwm4_groups[] = { "pwm4_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2412,6 +2480,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 1fdafa48479c..8c06d7275389 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -23,8 +23,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS) /* @@ -1299,6 +1303,169 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 8), +}; + +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; + +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B_A */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; + +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B_B */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; + +static const unsigned int audio_clk_b_c_pins[] = { + /* CLK B_C */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int audio_clk_b_c_mux[] = { + AUDIO_CLKB_C_MARK, +}; + +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C_A */ + RCAR_GP_PIN(5, 16), +}; + +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; + +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C_B */ + RCAR_GP_PIN(6, 3), +}; + +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; + +static const unsigned int audio_clk_c_c_pins[] = { + /* CLK C_C */ + RCAR_GP_PIN(6, 14), +}; + +static const unsigned int audio_clk_c_c_mux[] = { + AUDIO_CLKC_C_MARK, +}; + +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT_A */ + RCAR_GP_PIN(5, 3), +}; + +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; + +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT_B */ + RCAR_GP_PIN(5, 13), +}; + +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; + +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1_A */ + RCAR_GP_PIN(5, 4), +}; + +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; + +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1_B */ + RCAR_GP_PIN(5, 5), +}; + +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; + +static const unsigned int audio_clkout1_c_pins[] = { + /* CLKOUT1_C */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int audio_clkout1_c_mux[] = { + AUDIO_CLKOUT1_C_MARK, +}; + +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2_A */ + RCAR_GP_PIN(5, 8), +}; + +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; + +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2_B */ + RCAR_GP_PIN(6, 4), +}; + +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; + +static const unsigned int audio_clkout2_c_pins[] = { + /* CLKOUT2_C */ + RCAR_GP_PIN(6, 15), +}; + +static const unsigned int audio_clkout2_c_mux[] = { + AUDIO_CLKOUT2_C_MARK, +}; + +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3_A */ + RCAR_GP_PIN(5, 9), +}; + +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; + +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3_B */ + RCAR_GP_PIN(5, 6), +}; + +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + +static const unsigned int audio_clkout3_c_pins[] = { + /* CLKOUT3_C */ + RCAR_GP_PIN(6, 16), +}; + +static const unsigned int audio_clkout3_c_mux[] = { + AUDIO_CLKOUT3_C_MARK, +}; + /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { /* AVB_LINK */ @@ -1371,6 +1538,54 @@ static const unsigned int avb_avtp_capture_a_mux[] = { AVB_AVTP_CAPTURE_A_MARK, }; +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; + +static const unsigned int can0_data_mux[] = { + CAN0_TX_MARK, CAN0_RX_MARK, +}; + +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(0, 14), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; + +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; + +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -1459,6 +1674,290 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HSCIF0 --------------------------------------------------*/ +static const unsigned int hscif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; + +static const unsigned int hscif0_data_a_mux[] = { + HRX0_A_MARK, HTX0_A_MARK, +}; + +static const unsigned int hscif0_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int hscif0_clk_a_mux[] = { + HSCK0_A_MARK, +}; + +static const unsigned int hscif0_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), +}; + +static const unsigned int hscif0_ctrl_a_mux[] = { + HRTS0_N_A_MARK, HCTS0_N_A_MARK, +}; + +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; + +static const unsigned int hscif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int hscif0_clk_b_mux[] = { + HSCK0_B_MARK, +}; + +/* - HSCIF1 ------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; + +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), +}; + +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; + +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; + +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; + +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), +}; + +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; + +/* - HSCIF2 ------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), +}; + +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; + +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 14), +}; + +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; + +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; + +/* - HSCIF3 ------------------------------------------------*/ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; + +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; + +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; + +static const unsigned int hscif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; + +static const unsigned int hscif3_clk_b_mux[] = { + HSCK3_B_MARK, +}; + +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), +}; + +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; + +static const unsigned int hscif3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 11), +}; + +static const unsigned int hscif3_clk_c_mux[] = { + HSCK3_C_MARK, +}; + +static const unsigned int hscif3_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), +}; + +static const unsigned int hscif3_ctrl_c_mux[] = { + HRTS3_N_C_MARK, HCTS3_N_C_MARK, +}; + +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), +}; + +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; + +static const unsigned int hscif3_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; + +static const unsigned int hscif3_data_e_mux[] = { + HRX3_E_MARK, HTX3_E_MARK, +}; + +static const unsigned int hscif3_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), +}; + +static const unsigned int hscif3_ctrl_e_mux[] = { + HRTS3_N_E_MARK, HCTS3_N_E_MARK, +}; + +/* - HSCIF4 -------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), +}; + +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; + +static const unsigned int hscif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 0), +}; + +static const unsigned int hscif4_clk_a_mux[] = { + HSCK4_A_MARK, +}; + +static const unsigned int hscif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int hscif4_ctrl_a_mux[] = { + HRTS4_N_A_MARK, HCTS4_N_A_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), +}; + +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + +static const unsigned int hscif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 6), +}; + +static const unsigned int hscif4_clk_b_mux[] = { + HSCK4_B_MARK, +}; + +static const unsigned int hscif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; + +static const unsigned int hscif4_data_c_mux[] = { + HRX4_C_MARK, HTX4_C_MARK, +}; + +static const unsigned int hscif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int hscif4_data_d_mux[] = { + HRX4_D_MARK, HTX4_D_MARK, +}; + +static const unsigned int hscif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; + +static const unsigned int hscif4_data_e_mux[] = { + HRX4_E_MARK, HTX4_E_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SCL, SDA */ @@ -2386,6 +2885,364 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; + +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; + +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; + +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; + +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; + +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; + +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; + +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; + +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; + +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; + +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; + +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; + +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; + +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; + +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; + +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; + +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; + +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; + +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; + +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; + +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; + +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; + +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; + +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; + +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; + +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; + +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; + +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; + +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 10), +}; + +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; + +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; + +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; + +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK01239_MARK, SSI_WS01239_MARK, +}; + +static const unsigned int ssi1_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; + +static const unsigned int ssi1_data_mux[] = { + SSI_SDATA1_MARK, +}; + +static const unsigned int ssi1_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int ssi1_ctrl_mux[] = { + SSI_SCK1_MARK, SSI_WS1_MARK, +}; + +static const unsigned int ssi2_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; + +static const unsigned int ssi2_data_mux[] = { + SSI_SDATA2_MARK, +}; + +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; + +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; + +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; + +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; + +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; + +static const unsigned int ssi349_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; + +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, +}; + +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; + +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; + +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), +}; + +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; + +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; + +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; + +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; + +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; + +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; + +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; + +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; + +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), +}; + +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; + +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; + +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; + +static const unsigned int ssi9_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 16), +}; + +static const unsigned int ssi9_data_mux[] = { + SSI_SDATA9_MARK, +}; + +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), +}; + +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; + +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_a_pins[] = { /* PWEN, OVC */ @@ -2433,11 +3290,261 @@ static const unsigned int usb30_id_mux[] = { USB3HS0_ID_MARK, }; +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_a_pins[] = { + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const union vin_data vin4_data_a_pins = { + .data24 = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), + }, +}; + +static const union vin_data vin4_data_a_mux = { + .data24 = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; + +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const union vin_data vin4_data_b_pins = { + .data24 = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), + }, +}; + +static const union vin_data vin4_data_b_mux = { + .data24 = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, + }, +}; + +static const unsigned int vin4_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), +}; + +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; + +static const unsigned int vin4_field_pins[] = { + RCAR_GP_PIN(2, 23), +}; + +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; + +static const unsigned int vin4_clkenb_pins[] = { + RCAR_GP_PIN(1, 2), +}; + +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; + +static const unsigned int vin4_clk_pins[] = { + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const union vin_data16 vin5_data_a_pins = { + .data16 = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + }, +}; + +static const union vin_data16 vin5_data_a_mux = { + .data16 = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, + }, +}; + +static const unsigned int vin5_data8_b_pins[] = { + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), +}; + +static const unsigned int vin5_data8_b_mux[] = { + VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, + VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, + VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, + VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, +}; + +static const unsigned int vin5_sync_a_pins[] = { + /* HSYNC_N, VSYNC_N */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), +}; + +static const unsigned int vin5_sync_a_mux[] = { + VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, +}; + +static const unsigned int vin5_field_a_pins[] = { + RCAR_GP_PIN(1, 10), +}; + +static const unsigned int vin5_field_a_mux[] = { + VI5_FIELD_A_MARK, +}; + +static const unsigned int vin5_clkenb_a_pins[] = { + RCAR_GP_PIN(0, 1), +}; + +static const unsigned int vin5_clkenb_a_mux[] = { + VI5_CLKENB_A_MARK, +}; + +static const unsigned int vin5_clk_a_pins[] = { + RCAR_GP_PIN(1, 0), +}; + +static const unsigned int vin5_clk_a_mux[] = { + VI5_CLK_A_MARK, +}; + +static const unsigned int vin5_clk_b_pins[] = { + RCAR_GP_PIN(2, 22), +}; + +static const unsigned int vin5_clk_b_mux[] = { + VI5_CLK_B_MARK, +}; + static const struct { - struct sh_pfc_pin_group common[123]; - struct sh_pfc_pin_group automotive[0]; + struct sh_pfc_pin_group common[241]; + struct sh_pfc_pin_group automotive[2]; } pinmux_groups = { .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_b_c), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clk_c_c), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout1_c), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout2_c), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(audio_clkout3_c), SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -2445,6 +3552,9 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_in_0), @@ -2454,6 +3564,37 @@ static const struct { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_clk_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_clk_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_clk_c), + SH_PFC_PIN_GROUP(hscif3_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif3_data_e), + SH_PFC_PIN_GROUP(hscif3_ctrl_e), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk_a), + SH_PFC_PIN_GROUP(hscif4_ctrl_a), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(hscif4_clk_b), + SH_PFC_PIN_GROUP(hscif4_data_c), + SH_PFC_PIN_GROUP(hscif4_data_d), + SH_PFC_PIN_GROUP(hscif4_data_e), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c1_c), @@ -2556,14 +3697,105 @@ static const struct { SH_PFC_PIN_GROUP(scif5_data_c), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), SH_PFC_PIN_GROUP(usb0_a), SH_PFC_PIN_GROUP(usb0_b), SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 8, _a), + VIN_DATA_PIN_GROUP(vin5_data, 10, _a), + VIN_DATA_PIN_GROUP(vin5_data, 12, _a), + VIN_DATA_PIN_GROUP(vin5_data, 16, _a), + SH_PFC_PIN_GROUP(vin5_data8_b), + SH_PFC_PIN_GROUP(vin5_sync_a), + SH_PFC_PIN_GROUP(vin5_field_a), + SH_PFC_PIN_GROUP(vin5_clkenb_a), + SH_PFC_PIN_GROUP(vin5_clk_a), + SH_PFC_PIN_GROUP(vin5_clk_b), + }, + .automotive = { + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), } }; +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_b_c", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clk_c_c", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout1_c", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout2_c", + "audio_clkout3_a", + "audio_clkout3_b", + "audio_clkout3_c", +}; + static const char * const avb_groups[] = { "avb_link", "avb_magic", @@ -2574,6 +3806,26 @@ static const char * const avb_groups[] = { "avb_avtp_capture_a", }; +static const char * const can0_groups[] = { + "can0_data", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -2586,6 +3838,52 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_clk_a", + "hscif0_ctrl_a", + "hscif0_data_b", + "hscif0_clk_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_data_b", + "hscif3_clk_b", + "hscif3_data_c", + "hscif3_clk_c", + "hscif3_ctrl_c", + "hscif3_data_d", + "hscif3_data_e", + "hscif3_ctrl_e", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk_a", + "hscif4_ctrl_a", + "hscif4_data_b", + "hscif4_clk_b", + "hscif4_data_c", + "hscif4_data_d", + "hscif4_data_e", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -2763,6 +4061,56 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data", + "ssi1_ctrl", + "ssi2_data", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi349_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + static const char * const usb0_groups[] = { "usb0_a", "usb0_b", @@ -2774,13 +4122,56 @@ static const char * const usb30_groups[] = { "usb30_id", }; +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data18_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data18_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8_a", + "vin5_data10_a", + "vin5_data12_a", + "vin5_data16_a", + "vin5_data8_b", + "vin5_sync_a", + "vin5_field_a", + "vin5_clkenb_a", + "vin5_clk_a", + "vin5_clk_b", +}; + static const struct { - struct sh_pfc_function common[29]; - struct sh_pfc_function automotive[0]; + struct sh_pfc_function common[44]; + struct sh_pfc_function automotive[2]; } pinmux_functions = { .common = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c4), @@ -2806,8 +4197,18 @@ static const struct { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), + }, + .automotive = { + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), } }; @@ -3280,6 +4681,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +enum ioctrl_regs { + IOCTRL30, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [IOCTRL30] = { 0xe6060380, }, + { /* sentinel */ }, +}; + +static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) + bit = pin & 0x1f; + + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) + bit = (pin & 0x1f) + 19; + + return bit; +} + static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { [0] = RCAR_GP_PIN(2, 23), /* RD# */ @@ -3530,6 +4956,7 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, } static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { + .pin_to_pocctrl = r8a77990_pin_to_pocctrl, .get_bias = r8a77990_pinmux_get_bias, .set_bias = r8a77990_pinmux_set_bias, }; @@ -3551,6 +4978,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .cfg_regs = pinmux_config_regs, .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index 9484eaa8522a..e457539a61c5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -468,12 +468,6 @@ enum { #undef FM }; -#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ - PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr) - -#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ - PINMUX_DATA(fn##_MARK, FN_##msel) - static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 458ae0a6b540..78dc342d7b39 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -53,18 +53,32 @@ struct sh_pfc_pin_group { }; /* - * Using union vin_data saves memory occupied by the VIN data pins. - * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups - * in this case. + * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. + * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups + * in this case. It accepts an optional 'version' argument used when the + * same group can appear on a different set of pins. */ -#define VIN_DATA_PIN_GROUP(n, s) \ - { \ - .name = #n#s, \ - .pins = n##_pins.data##s, \ - .mux = n##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ +#define VIN_DATA_PIN_GROUP(n, s, ...) \ + { \ + .name = #n#s#__VA_ARGS__, \ + .pins = n##__VA_ARGS__##_pins.data##s, \ + .mux = n##__VA_ARGS__##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ } +union vin_data12 { + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; +}; + +union vin_data16 { + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; +}; + union vin_data { unsigned int data24[24]; unsigned int data20[20]; @@ -372,6 +386,28 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) +/* + * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with + * an additional select register that controls physical multiplexing + * with another pin. + * - ipsr: IPSR field + * - fn: Function name, also referring to the IPSR field + * - psel: Physical multiplexing selector + * - msel: Module selector + */ +#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ + PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) + +/* + * Describe a pinmux configuration in which a pin is physically multiplexed + * with other pins. + * - ipsr: IPSR field + * - fn: Function name, also referring to the IPSR field + * - psel: Physical multiplexing selector + */ +#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ + PINMUX_DATA(fn##_MARK, FN_##psel) + /* * Describe a pinmux configuration for a single-function pin with GPIO * capability. diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h new file mode 100644 index 000000000000..2d0c23e5d3a7 --- /dev/null +++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/A2 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H +#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H + +#define RZA2_PINS_PER_PORT 8 + +/* Port names as labeled in the Hardware Manual */ +#define PORT0 0 +#define PORT1 1 +#define PORT2 2 +#define PORT3 3 +#define PORT4 4 +#define PORT5 5 +#define PORT6 6 +#define PORT7 7 +#define PORT8 8 +#define PORT9 9 +#define PORTA 10 +#define PORTB 11 +#define PORTC 12 +#define PORTD 13 +#define PORTE 14 +#define PORTF 15 +#define PORTG 16 +#define PORTH 17 +/* No I */ +#define PORTJ 18 +#define PORTK 19 +#define PORTL 20 +#define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */ + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16)) + +/* + * Convert a port and pin label to its global pin index + */ + #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */