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clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling 

[ Upstream commit b311f5d3c4 ]

Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.

Fixes: 1c9efb0bc0 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Imran Shaik 2023-08-03 16:27:35 +05:30 committed by Greg Kroah-Hartman
parent cbfd73886e
commit 84fbbb177d
1 changed files with 6 additions and 17 deletions
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23
drivers/clk/qcom/gcc-qdu1000.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_TCXO_IDX },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_PCIE_0_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_PCIE_0_PIPE_CLK_IDX },
{ .index = DT_TCXO_IDX },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
},
};
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_0_PIPE_CLK_IDX,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},