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clk: shmobile: rcar-gen2: Fix qspi divisor
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -215,7 +215,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
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} else if (!strcmp(name, "qspi")) {
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parent_name = "pll1_div2";
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div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
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? 16 : 20;
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? 8 : 10;
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} else if (!strcmp(name, "sdh")) {
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parent_name = "pll1_div2";
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table = cpg_sdh_div_table;
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