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gpio: aspeed: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20190809125515.19094-1-linus.walleij@linaro.org Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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parent
a2ac3eb365
commit
8512ee3192
1 changed files with 29 additions and 31 deletions
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@ -711,32 +711,6 @@ static void set_irq_valid_mask(struct aspeed_gpio *gpio)
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}
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}
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static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
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struct platform_device *pdev)
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{
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int rc;
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rc = platform_get_irq(pdev, 0);
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if (rc < 0)
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return rc;
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gpio->irq = rc;
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set_irq_valid_mask(gpio);
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rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip,
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0, handle_bad_irq, IRQ_TYPE_NONE);
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if (rc) {
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dev_info(&pdev->dev, "Could not add irqchip\n");
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return rc;
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}
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gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip,
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gpio->irq, aspeed_gpio_irq_handler);
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return 0;
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}
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static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
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unsigned int offset, bool enable)
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{
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@ -1189,7 +1163,6 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
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gpio->chip.set_config = aspeed_gpio_set_config;
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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gpio->chip.irq.need_valid_mask = true;
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/* Allocate a cache of the output registers */
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banks = gpio->config->nr_gpios >> 5;
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@ -1212,16 +1185,41 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
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aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
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}
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rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
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if (rc < 0)
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return rc;
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/* Optionally set up an irqchip if there is an IRQ */
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rc = platform_get_irq(pdev, 0);
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if (rc > 0) {
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struct gpio_irq_chip *girq;
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gpio->irq = rc;
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girq = &gpio->chip.irq;
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girq->chip = &aspeed_gpio_irqchip;
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girq->parent_handler = aspeed_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = gpio->irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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girq->need_valid_mask = true;
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}
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gpio->offset_timer =
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devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
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if (!gpio->offset_timer)
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return -ENOMEM;
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return aspeed_gpio_setup_irqs(gpio, pdev);
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rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
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if (rc < 0)
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return rc;
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/* Now the valid mask is allocated */
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if (gpio->irq)
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set_irq_valid_mask(gpio);
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return 0;
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}
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static struct platform_driver aspeed_gpio_driver = {
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