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Samsung DTS ARM changes for v4.19

Browse source 
1. Add two new S5Pv210 boards: Samsung Galaxy S and Samsung Galaxy S 4G
    mobile phones.  Both are from family codenamed Aries.  The Samsung
    Galaxy S was released on the market in 2010 with Android operating
    system.  At that time, it was the Samsung's flagship model.
    This brings support for storage (SD card and internal memory), PMIC,
    RTC, fuel-gauge, keys, USB (in peripherial mode) and WiFi.
 
 2. Add missing secondary CPU properties.
 3. Cleanup from old files and properties.
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Merge tag 'samsung-dt-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DTS ARM changes for v4.19

1. Add two new S5Pv210 boards: Samsung Galaxy S and Samsung Galaxy S 4G
   mobile phones.  Both are from family codenamed Aries.  The Samsung
   Galaxy S was released on the market in 2010 with Android operating
   system.  At that time, it was the Samsung's flagship model.
   This brings support for storage (SD card and internal memory), PMIC,
   RTC, fuel-gauge, keys, USB (in peripherial mode) and WiFi.

2. Add missing secondary CPU properties.
3. Cleanup from old files and properties.

* tag 'samsung-dt-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  dt-bindings: samsung: Document bindings for SGH-T959P board
  dt-bindings: samsung: Document bindings for Samsung aries boards
  ARM: dts: s5pv210: Add initial DTS for SGH-T959P phone
  ARM: dts: s5pv210: Add initial DTS for Samsung Galaxy S phone
  ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones
  ARM: dts: s5pv210: Add missing interrupt-controller property to gph2
  ARM: dts: exynos: remove no longer needed samsung thermal properties
  dt-bindings: arm: Remove obsolete insignal-boards.txt
  ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
  arm: dts: exynos: Add missing cooling device properties for CPUs

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-14 14:22:29 -07:00
commit 85b40cf3a8
18 changed files with 635 additions and 63 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/insignal-boards.txt
View file

@ -1,8 +0,0 @@
* Insignal's Exynos4210 based Origen evaluation board
Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
Required root node properties:
- compatible = should be one or more of the following.
(a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
(b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.

5
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View file

@ -1,7 +1,10 @@
* Samsung's Exynos SoC based boards
* Samsung's Exynos and S5P SoC based boards
Required root node properties:
- compatible = should be one or more of the following.
- "samsung,aries" - for S5PV210-based Samsung Aries board.
- "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
- "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.

2
arch/arm/boot/dts/Makefile
View file

@ -860,6 +860,8 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-aquila.dtb \
s5pv210-fascinate4g.dtb \
s5pv210-galaxys.dtb \
s5pv210-goni.dtb \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \

18
arch/arm/boot/dts/exynos3250.dtsi
View file

@ -78,6 +78,22 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
clocks = <&cmu CLK_ARM_CLK>;
clock-names = "cpu";
#cooling-cells = <2>;
operating-points = <
1000000 1150000
900000 1112500
800000 1075000
700000 1037500
600000 1000000
500000 962500
400000 925000
300000 887500
200000 850000
100000 850000
>;
};
};
@ -226,7 +242,7 @@ tmu: tmu@100c0000 {
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
status = "disabled";
};

2
arch/arm/boot/dts/exynos4.dtsi
View file

@ -735,7 +735,7 @@ tmu: tmu@100c0000 {
reg = <0x100C0000 0x100>;
interrupts = <2 4>;
status = "disabled";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
jpeg_codec: jpeg-codec@11840000 {

13
arch/arm/boot/dts/exynos4210.dtsi
View file

@ -55,6 +55,19 @@ cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
clock-latency = <160000>;
operating-points = <
1200000 1250000
1000000 1150000
800000 1075000
500000 975000
400000 975000
200000 950000
>;
#cooling-cells = <2>; /* min followed by max */
};
};

20
arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
View file

@ -1,20 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device tree sources for Exynos4412 TMU sensor configuration
*
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <8>;
samsung,tmu_reference_voltage = <16>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <55>;
samsung,tmu_min_efuse_value = <40>;
samsung,tmu_max_efuse_value = <100>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;

9
arch/arm/boot/dts/exynos4412.dtsi
View file

@ -49,21 +49,30 @@ cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@a02 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA02>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@a03 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA03>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
};

25
arch/arm/boot/dts/exynos5250.dtsi
View file

@ -84,6 +84,29 @@ cpu@1 {
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1700000000>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
clock-latency = <140000>;
operating-points = <
1700000 1300000
1600000 1250000
1500000 1225000
1400000 1200000
1300000 1150000
1200000 1125000
1100000 1100000
1000000 1075000
900000 1050000
800000 1025000
700000 1012500
600000 1000000
500000 975000
400000 950000
300000 937500
200000 925000
>;
#cooling-cells = <2>; /* min followed by max */
};
};
@ -278,7 +301,7 @@ tmu: tmu@10060000 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
sata: sata@122f0000 {

8
arch/arm/boot/dts/exynos5410.dtsi
View file

@ -93,7 +93,7 @@ tmu_cpu0: tmu@10060000 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu1: tmu@10064000 {
@ -102,7 +102,7 @@ tmu_cpu1: tmu@10064000 {
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu2: tmu@10068000 {
@ -111,7 +111,7 @@ tmu_cpu2: tmu@10068000 {
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu3: tmu@1006c000 {
@ -120,7 +120,7 @@ tmu_cpu3: tmu@1006c000 {
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
mmc_0: mmc@12200000 {

6
arch/arm/boot/dts/exynos5420-cpus.dtsi
View file

@ -38,6 +38,7 @@ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -49,6 +50,7 @@ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -60,6 +62,7 @@ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -83,6 +86,7 @@ cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@ -94,6 +98,7 @@ cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@ -105,6 +110,7 @@ cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;

21
arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi
View file

@ -1,21 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device tree sources for Exynos5420 TMU sensor configuration
*
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
* Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <8>;
samsung,tmu_reference_voltage = <16>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <55>;
samsung,tmu_min_efuse_value = <0>;
samsung,tmu_max_efuse_value = <100>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;

10
arch/arm/boot/dts/exynos5420.dtsi
View file

@ -738,7 +738,7 @@ tmu_cpu0: tmu@10060000 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu1: tmu@10064000 {
@ -747,7 +747,7 @@ tmu_cpu1: tmu@10064000 {
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu2: tmu@10068000 {
@ -756,7 +756,7 @@ tmu_cpu2: tmu@10068000 {
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_cpu3: tmu@1006c000 {
@ -765,7 +765,7 @@ tmu_cpu3: tmu@1006c000 {
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
tmu_gpu: tmu@100a0000 {
@ -774,7 +774,7 @@ tmu_gpu: tmu@100a0000 {
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
#thermal-sensor-cells = <0>;
};
sysmmu_g2dr: sysmmu@10a60000 {

8
arch/arm/boot/dts/exynos5422-cpus.dtsi
View file

@ -37,6 +37,7 @@ cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@ -48,6 +49,7 @@ cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@ -59,6 +61,7 @@ cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@ -69,8 +72,8 @@ cpu3: cpu@103 {
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -82,6 +85,7 @@ cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -93,6 +97,7 @@ cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@ -104,6 +109,7 @@ cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;

419
arch/arm/boot/dts/s5pv210-aries.dtsi Normal file
View file

@ -0,0 +1,419 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's S5PV210 based Galaxy Aries board device tree source
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "s5pv210.dtsi"
/ {
compatible = "samsung,aries", "samsung,s5pv210";
aliases {
i2c6 = &i2c_pmic;
i2c9 = &i2c_fuel;
};
memory@30000000 {
device_type = "memory";
reg = <0x30000000 0x05000000
0x40000000 0x10000000
0x50000000 0x08000000>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&wlan_gpio_rst>;
post-power-on-delay-ms = <500>;
power-off-delay-us = <500>;
};
i2c_pmic: i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
pmic@66 {
compatible = "maxim,max8998";
reg = <0x66>;
interrupt-parent = <&gph0>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
max8998,pmic-buck1-default-dvs-idx = <1>;
max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>,
<&gph0 4 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>,
<1050000>, <950000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>;
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
ldo3_reg: LDO3 {
regulator-name = "VUSB_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo4_reg: LDO4 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo5_reg: LDO5 {
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo6_reg: LDO6 {
regulator-name = "LDO6";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3600000>;
};
ldo7_reg: LDO7 {
regulator-name = "VLCD_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* Till we get panel driver */
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo8_reg: LDO8 {
regulator-name = "VUSB_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo9_reg: LDO9 {
regulator-name = "VCC_2.8V_PDA";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "VPLL_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
ldo11_reg: LDO11 {
regulator-name = "CAM_AF_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo12_reg: LDO12 {
regulator-name = "CAM_SENSOR_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo13_reg: LDO13 {
regulator-name = "VGA_VDDIO_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo14_reg: LDO14 {
regulator-name = "VGA_DVDD_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo15_reg: LDO15 {
regulator-name = "CAM_ISP_HOST_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo16_reg: LDO16 {
regulator-name = "VGA_AVDD_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo17_reg: LDO17 {
regulator-name = "VCC_3.0V_LCD";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
/* Till we get panel driver */
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck1_reg: BUCK1 {
regulator-name = "vddarm";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1250000>;
};
};
buck2_reg: BUCK2 {
regulator-name = "vddint";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1100000>;
};
};
buck3_reg: BUCK3 {
regulator-name = "VCC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "CAM_ISP_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ap32khz_reg: EN32KHz-AP {
regulator-name = "32KHz AP";
regulator-always-on;
};
cp32khz_reg: EN32KHz-CP {
regulator-name = "32KHz CP";
};
vichg_reg: ENVICHG {
regulator-name = "VICHG";
regulator-always-on;
};
safe1_sreg: ESAFEOUT1 {
regulator-name = "SAFEOUT1";
};
safe2_sreg: ESAFEOUT2 {
regulator-name = "SAFEOUT2";
};
};
};
};
i2c_fuel: i2c-gpio-1 {
compatible = "i2c-gpio";
sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
fuelgauge@36 {
compatible = "maxim,max17040";
interrupt-parent = <&vic0>;
interrupts = <7>;
reg = <0x36>;
};
};
};
&fimd {
pinctrl-names = "default";
pinctrl-0 = <&lcd_clk &lcd_data24>;
status = "okay";
samsung,invert-vden;
samsung,invert-vclk;
display-timings {
timing-0 {
/* 480x800@60Hz */
clock-frequency = <25628040>;
hactive = <480>;
vactive = <800>;
hfront-porch = <16>;
hback-porch = <16>;
hsync-len = <2>;
vfront-porch = <28>;
vback-porch = <1>;
vsync-len = <2>;
};
};
};
&hsotg {
vusb_a-supply = <&ldo8_reg>;
vusb_d-supply = <&ldo3_reg>;
dr_mode = "peripheral";
status = "okay";
};
&pinctrl0 {
wlan_bt_en: wlan-bt-en {
samsung,pins = "gpb-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-val = <1>;
};
wlan_gpio_rst: wlan-gpio-rst {
samsung,pins = "gpg1-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
wifi_host_wake: wifi-host-wake {
samsung,pins = "gph2-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
tf_detect: tf-detect {
samsung,pins = "gph3-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
wifi_wake: wifi-wake {
samsung,pins = "gph3-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
};
&sdhci1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
max-frequency = <38400000>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>;
pinctrl-names = "default";
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
wlan@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gph2>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&ldo5_reg>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>;
pinctrl-names = "default";
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&usbphy {
status = "okay";
vbus-supply = <&safe1_sreg>;
};
&xusbxti {
clock-frequency = <24000000>;
};

45
arch/arm/boot/dts/s5pv210-fascinate4g.dts Normal file
View file

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "s5pv210-aries.dtsi"
/ {
model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210";
compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210";
chosen {
stdout-path = &uart2;
/*
* It's hard to change those parameters in stock bootloader,
* since it requires special hardware/cable.
* Let's hardocde bootargs for now, till u-boot port is finished,
* with which it should be easier.
*/
bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk";
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "power";
gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
vol-down {
label = "volume_down";
gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
vol-up {
label = "volume_up";
gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
};

77
arch/arm/boot/dts/s5pv210-galaxys.dts Normal file
View file

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "s5pv210-aries.dtsi"
/ {
model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210";
compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210";
chosen {
stdout-path = &uart2;
/*
* It's hard to change those parameters in stock bootloader,
* since it requires special hardware/cable.
* Let's hardocde bootargs for now, till u-boot port is finished,
* with which it should be easier.
*/
bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk";
};
nand_pwrseq: nand-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&massmemory_en>;
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "power";
gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
vol-down {
label = "volume_down";
gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
vol-up {
label = "volume_up";
gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
home {
label = "home";
gpios = <&gph3 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
};
};
&pinctrl0 {
massmemory_en: massmemory-en {
samsung,pins = "gpj2-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
&sdhci0 {
bus-width = <4>;
non-removable;
mmc-pwrseq = <&nand_pwrseq>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm/boot/dts/s5pv210-pinctrl.dtsi
View file

@ -258,6 +258,8 @@ gph1: gph1 {
gph2: gph2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};