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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
sh-pfc: Remove configuration dry-run and free
The purpose of the dry-run is to ensure that a pin about to be configured isn't in use. However, the current implementation is a no-op. This proves that the dry-run isn't essential. Remove it. Freeing configuration then becomes a no-op as well. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
1a0039dce2
commit
861601de10
5 changed files with 12 additions and 108 deletions
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@ -163,22 +163,6 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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}
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}
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static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long field)
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{
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void __iomem *mapped_reg;
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unsigned long mask, pos;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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pr_debug("read_reg: addr = %lx, field = %ld, "
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"r_width = %ld, f_width = %ld\n",
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crp->reg, field, crp->reg_width, crp->field_width);
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return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
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}
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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long field, unsigned long value)
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@ -209,7 +193,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
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struct pinmux_cfg_reg **crp, int *fieldp,
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int *valuep, unsigned long **cntp)
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int *valuep)
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{
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struct pinmux_cfg_reg *config_reg;
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unsigned long r_width, f_width, curr_width, ncomb;
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@ -239,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
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*crp = config_reg;
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*fieldp = m;
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*valuep = n;
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*cntp = &config_reg->cnt[m];
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return 0;
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}
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}
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@ -274,14 +257,12 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
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return -1;
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}
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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int cfg_mode)
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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{
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struct pinmux_cfg_reg *cr = NULL;
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pinmux_enum_t enum_id;
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struct pinmux_range *range;
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int in_range, pos, field, value;
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unsigned long *cntp;
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switch (pinmux_type) {
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@ -306,7 +287,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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break;
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default:
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goto out_err;
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return -1;
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}
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pos = 0;
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@ -316,7 +297,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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while (1) {
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pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
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if (pos <= 0)
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goto out_err;
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return -1;
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if (!enum_id)
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break;
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@ -360,30 +341,13 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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continue;
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if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
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&field, &value, &cntp) != 0)
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goto out_err;
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&field, &value) != 0)
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return -1;
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switch (cfg_mode) {
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case GPIO_CFG_DRYRUN:
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if (!*cntp ||
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(sh_pfc_read_config_reg(pfc, cr, field) != value))
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continue;
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break;
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case GPIO_CFG_REQ:
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sh_pfc_write_config_reg(pfc, cr, field, value);
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*cntp = *cntp + 1;
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break;
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case GPIO_CFG_FREE:
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*cntp = *cntp - 1;
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break;
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}
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sh_pfc_write_config_reg(pfc, cr, field, value);
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}
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return 0;
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out_err:
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return -1;
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}
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static int sh_pfc_probe(struct platform_device *pdev)
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@ -52,8 +52,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
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unsigned long data);
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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int cfg_mode);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
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extern struct sh_pfc_soc_info r8a7740_pinmux_info;
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extern struct sh_pfc_soc_info r8a7779_pinmux_info;
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@ -285,10 +285,7 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
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spin_lock_irqsave(&pfc->lock, flags);
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if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN))
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goto done;
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if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ))
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if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION))
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goto done;
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ret = 0;
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@ -300,15 +297,6 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
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static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
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{
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struct sh_pfc *pfc = gpio_to_pfc(gc);
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unsigned int mark = pfc->info->func_gpios[offset].enum_id;
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unsigned long flags;
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spin_lock_irqsave(&pfc->lock, flags);
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sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int gpio_function_setup(struct sh_pfc_chip *chip)
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@ -119,12 +119,7 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i) {
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if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
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GPIO_CFG_DRYRUN))
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goto done;
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if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
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GPIO_CFG_REQ))
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if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION))
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goto done;
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}
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@ -138,19 +133,6 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
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static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i)
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sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
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GPIO_CFG_FREE);
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
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@ -166,32 +148,18 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
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spin_lock_irqsave(&pfc->lock, flags);
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/*
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* See if the present config needs to first be de-configured.
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*/
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switch (cfg->type) {
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case PINMUX_TYPE_GPIO:
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break;
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case PINMUX_TYPE_OUTPUT:
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case PINMUX_TYPE_INPUT:
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case PINMUX_TYPE_INPUT_PULLUP:
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case PINMUX_TYPE_INPUT_PULLDOWN:
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sh_pfc_config_mux(pfc, mark, cfg->type, GPIO_CFG_FREE);
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break;
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default:
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goto err;
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}
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/*
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* Dry run
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*/
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if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0)
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goto err;
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/*
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* Request
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*/
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if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
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if (sh_pfc_config_mux(pfc, mark, new_type) != 0)
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goto err;
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cfg->type = new_type;
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@ -241,18 +209,6 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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unsigned long flags;
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spin_lock_irqsave(&pfc->lock, flags);
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sh_pfc_config_mux(pfc, pin->enum_id, cfg->type, GPIO_CFG_FREE);
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
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@ -84,19 +84,16 @@ struct pinmux_func {
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struct pinmux_cfg_reg {
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unsigned long reg, reg_width, field_width;
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unsigned long *cnt;
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pinmux_enum_t *enum_ids;
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unsigned long *var_field_width;
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};
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#define PINMUX_CFG_REG(name, r, r_width, f_width) \
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.reg = r, .reg_width = r_width, .field_width = f_width, \
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.cnt = (unsigned long [r_width / f_width]) {}, \
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.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
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#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
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.reg = r, .reg_width = r_width, \
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.cnt = (unsigned long [r_width]) {}, \
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.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
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.enum_ids = (pinmux_enum_t [])
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@ -155,7 +152,7 @@ struct sh_pfc_soc_info {
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unsigned long unlock_reg;
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};
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enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
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enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
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/* helper macro for port */
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#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
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