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Merge branch 'icc-ip0-migration' into icc-next
Commits2f3724930e("interconnect: qcom: sc7180: Drop IP0 interconnects") and2fb251c265("interconnect: qcom: sdx55: Drop IP0 interconnects") removed IP0 interconnects (and ipa-virt devices support) in favour of the RPMH clocks. Follow this example for other platforms defining IP0 RPMH resource. While we are at it, remove several leftover from the mentioned patches. * icc-ip0-migration: interconnect: qcom: sdx55: drop IP0 remnants interconnect: qcom: sc7180: drop IP0 remnants interconnect: move ignore_list out of of_count_icc_providers() interconnect: qcom: sm8150: Drop IP0 interconnects interconnect: qcom: sm8250: Drop IP0 interconnects interconnect: qcom: sc8180x: Drop IP0 interconnects interconnect: qcom: sc8280xp: Drop IP0 interconnects dt-bindings: interconnect: qcom: Remove ipa-virt compatibles dt-bindings: interconnect: qcom: drop IPA_CORE related defines Link: https://lore.kernel.org/r/20230109002935.244320-1-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
863ed40ea9
18 changed files with 23 additions and 141 deletions
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@ -58,7 +58,6 @@ properties:
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- qcom,sc8180x-config-noc
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- qcom,sc8180x-dc-noc
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- qcom,sc8180x-gem-noc
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- qcom,sc8180x-ipa-virt
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- qcom,sc8180x-mc-virt
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- qcom,sc8180x-mmss-noc
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- qcom,sc8180x-qup-virt
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@ -96,7 +95,6 @@ properties:
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- qcom,sm8150-config-noc
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- qcom,sm8150-dc-noc
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- qcom,sm8150-gem-noc
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- qcom,sm8150-ipa-virt
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- qcom,sm8150-mc-virt
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- qcom,sm8150-mmss-noc
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- qcom,sm8150-system-noc
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@ -106,7 +104,6 @@ properties:
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- qcom,sm8250-config-noc
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- qcom,sm8250-dc-noc
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- qcom,sm8250-gem-noc
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- qcom,sm8250-ipa-virt
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- qcom,sm8250-mc-virt
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- qcom,sm8250-mmss-noc
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- qcom,sm8250-npu-noc
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@ -1079,15 +1079,19 @@ void icc_provider_del(struct icc_provider *provider)
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}
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EXPORT_SYMBOL_GPL(icc_provider_del);
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static const struct of_device_id __maybe_unused ignore_list[] = {
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{ .compatible = "qcom,sc7180-ipa-virt" },
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{ .compatible = "qcom,sc8180x-ipa-virt" },
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{ .compatible = "qcom,sdx55-ipa-virt" },
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{ .compatible = "qcom,sm8150-ipa-virt" },
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{ .compatible = "qcom,sm8250-ipa-virt" },
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{}
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};
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static int of_count_icc_providers(struct device_node *np)
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{
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struct device_node *child;
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int count = 0;
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const struct of_device_id __maybe_unused ignore_list[] = {
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{ .compatible = "qcom,sc7180-ipa-virt" },
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{ .compatible = "qcom,sdx55-ipa-virt" },
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{}
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};
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for_each_available_child_of_node(np, child) {
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if (of_property_read_bool(child, "#interconnect-cells") &&
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@ -11,7 +11,7 @@
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#define SC7180_MASTER_APPSS_PROC 0
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#define SC7180_MASTER_SYS_TCU 1
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#define SC7180_MASTER_NPU_SYS 2
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#define SC7180_MASTER_IPA_CORE 3
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/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */
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#define SC7180_MASTER_LLCC 4
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#define SC7180_MASTER_A1NOC_CFG 5
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#define SC7180_MASTER_A2NOC_CFG 6
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@ -58,7 +58,7 @@
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#define SC7180_MASTER_USB3 47
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#define SC7180_MASTER_EMMC 48
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#define SC7180_SLAVE_EBI1 49
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#define SC7180_SLAVE_IPA_CORE 50
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/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC7180_SLAVE_A1NOC_CFG 51
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#define SC7180_SLAVE_A2NOC_CFG 52
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#define SC7180_SLAVE_AHB2PHY_SOUTH 53
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@ -469,15 +469,6 @@ static struct qcom_icc_node mas_qxm_ecc = {
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.links = { SC8180X_SLAVE_LLCC }
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};
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static struct qcom_icc_node mas_ipa_core_master = {
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.name = "mas_ipa_core_master",
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.id = SC8180X_MASTER_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_SLAVE_IPA_CORE }
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};
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static struct qcom_icc_node mas_llcc_mc = {
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.name = "mas_llcc_mc",
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.id = SC8180X_MASTER_LLCC,
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@ -1201,13 +1192,6 @@ static struct qcom_icc_node slv_srvc_gemnoc1 = {
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.buswidth = 4
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};
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static struct qcom_icc_node slv_ipa_core_slave = {
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.name = "slv_ipa_core_slave",
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.id = SC8180X_SLAVE_IPA_CORE,
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.channels = 1,
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.buswidth = 8
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};
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static struct qcom_icc_node slv_ebi = {
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.name = "slv_ebi",
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.id = SC8180X_SLAVE_EBI_CH0,
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@ -1524,11 +1508,6 @@ static struct qcom_icc_bcm bcm_co2 = {
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.nodes = { &mas_qnm_npu }
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};
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static struct qcom_icc_bcm bcm_ip0 = {
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.name = "IP0",
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.nodes = { &slv_ipa_core_slave }
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};
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static struct qcom_icc_bcm bcm_sn3 = {
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.name = "SN3",
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.keepalive = true,
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@ -1604,10 +1583,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = {
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&bcm_sh3,
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};
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static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
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&bcm_ip0,
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};
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static struct qcom_icc_bcm * const mc_virt_bcms[] = {
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&bcm_mc0,
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&bcm_acv,
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@ -1766,11 +1741,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
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[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
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};
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static struct qcom_icc_node * const ipa_virt_nodes[] = {
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[MASTER_IPA_CORE] = &mas_ipa_core_master,
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[SLAVE_IPA_CORE] = &slv_ipa_core_slave,
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};
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static struct qcom_icc_node * const mc_virt_nodes[] = {
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[MASTER_LLCC] = &mas_llcc_mc,
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[SLAVE_EBI_CH0] = &slv_ebi,
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@ -1857,13 +1827,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = {
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.num_bcms = ARRAY_SIZE(gem_noc_bcms),
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};
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static const struct qcom_icc_desc sc8180x_ipa_virt = {
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.nodes = ipa_virt_nodes,
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.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
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.bcms = ipa_virt_bcms,
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.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
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};
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static const struct qcom_icc_desc sc8180x_mc_virt = {
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.nodes = mc_virt_nodes,
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.num_nodes = ARRAY_SIZE(mc_virt_nodes),
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@ -1913,7 +1876,6 @@ static const struct of_device_id qnoc_of_match[] = {
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{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
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{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
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{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
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{ .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
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{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
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{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
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{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
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@ -51,7 +51,7 @@
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#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
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#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
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#define SC8180X_MASTER_ECC 43
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#define SC8180X_MASTER_IPA_CORE 44
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/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
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#define SC8180X_MASTER_LLCC 45
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#define SC8180X_MASTER_CNOC_MNOC_CFG 46
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#define SC8180X_MASTER_CAMNOC_HF0 47
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@ -146,7 +146,7 @@
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#define SC8180X_SLAVE_LLCC 136
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#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
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#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
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#define SC8180X_SLAVE_IPA_CORE 139
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/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8180X_SLAVE_EBI_CH0 140
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#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
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#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
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@ -284,15 +284,6 @@ static struct qcom_icc_node xm_ufs_card = {
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.links = { SC8280XP_SLAVE_A2NOC_SNOC },
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};
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static struct qcom_icc_node ipa_core_master = {
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.name = "ipa_core_master",
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.id = SC8280XP_MASTER_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_IPA_CORE },
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};
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static struct qcom_icc_node qup0_core_master = {
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.name = "qup0_core_master",
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.id = SC8280XP_MASTER_QUP_CORE_0,
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@ -882,13 +873,6 @@ static struct qcom_icc_node srvc_aggre2_noc = {
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.buswidth = 4,
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};
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static struct qcom_icc_node ipa_core_slave = {
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.name = "ipa_core_slave",
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.id = SC8280XP_SLAVE_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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};
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static struct qcom_icc_node qup0_core_slave = {
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.name = "qup0_core_slave",
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.id = SC8280XP_SLAVE_QUP_CORE_0,
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@ -1845,12 +1829,6 @@ static struct qcom_icc_bcm bcm_cn3 = {
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},
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};
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static struct qcom_icc_bcm bcm_ip0 = {
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.name = "IP0",
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.num_nodes = 1,
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.nodes = { &ipa_core_slave },
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};
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static struct qcom_icc_bcm bcm_mc0 = {
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.name = "MC0",
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.keepalive = true,
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@ -2077,18 +2055,15 @@ static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
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};
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static struct qcom_icc_bcm * const clk_virt_bcms[] = {
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&bcm_ip0,
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&bcm_qup0,
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&bcm_qup1,
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&bcm_qup2,
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};
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static struct qcom_icc_node * const clk_virt_nodes[] = {
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[MASTER_IPA_CORE] = &ipa_core_master,
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[MASTER_QUP_CORE_1] = &qup1_core_master,
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[MASTER_QUP_CORE_2] = &qup2_core_master,
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[SLAVE_IPA_CORE] = &ipa_core_slave,
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[SLAVE_QUP_CORE_0] = &qup0_core_slave,
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[SLAVE_QUP_CORE_1] = &qup1_core_slave,
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[SLAVE_QUP_CORE_2] = &qup2_core_slave,
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@ -10,7 +10,7 @@
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#define SC8280XP_MASTER_PCIE_TCU 1
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#define SC8280XP_MASTER_SYS_TCU 2
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#define SC8280XP_MASTER_APPSS_PROC 3
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#define SC8280XP_MASTER_IPA_CORE 4
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/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8280XP_MASTER_LLCC 5
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#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
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#define SC8280XP_MASTER_CDSP_NOC_CFG 7
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@ -84,7 +84,7 @@
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#define SC8280XP_MASTER_USB4_0 75
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#define SC8280XP_MASTER_USB4_1 76
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#define SC8280XP_SLAVE_EBI1 512
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#define SC8280XP_SLAVE_IPA_CORE 513
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/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8280XP_SLAVE_AHB2PHY_0 514
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#define SC8280XP_SLAVE_AHB2PHY_1 515
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#define SC8280XP_SLAVE_AHB2PHY_2 516
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@ -6,7 +6,7 @@
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
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#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
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#define SDX55_MASTER_IPA_CORE 0
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/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
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#define SDX55_MASTER_LLCC 1
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#define SDX55_MASTER_TCU_0 2
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#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
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@ -28,7 +28,7 @@
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#define SDX55_MASTER_QDSS_ETR 19
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#define SDX55_MASTER_SDCC_1 20
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#define SDX55_MASTER_USB3 21
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#define SDX55_SLAVE_IPA_CORE 22
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/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SDX55_SLAVE_EBI_CH0 23
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#define SDX55_SLAVE_LLCC 24
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#define SDX55_SLAVE_MEM_NOC_SNOC 25
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@ -56,7 +56,6 @@ DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC
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DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
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DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
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DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
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DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
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@ -139,7 +138,6 @@ DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
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DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
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DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
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DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
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DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
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DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
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DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
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@ -172,7 +170,6 @@ DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
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DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
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DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
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DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
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DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
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DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
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DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
|
||||
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
|
||||
|
|
@ -398,22 +395,6 @@ static const struct qcom_icc_desc sm8150_gem_noc = {
|
|||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
|
||||
&bcm_ip0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const ipa_virt_nodes[] = {
|
||||
[MASTER_IPA_CORE] = &ipa_core_master,
|
||||
[SLAVE_IPA_CORE] = &ipa_core_slave,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm8150_ipa_virt = {
|
||||
.nodes = ipa_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
|
||||
.bcms = ipa_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
|
|
@ -517,8 +498,6 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||
.data = &sm8150_dc_noc},
|
||||
{ .compatible = "qcom,sm8150-gem-noc",
|
||||
.data = &sm8150_gem_noc},
|
||||
{ .compatible = "qcom,sm8150-ipa-virt",
|
||||
.data = &sm8150_ipa_virt},
|
||||
{ .compatible = "qcom,sm8150-mc-virt",
|
||||
.data = &sm8150_mc_virt},
|
||||
{ .compatible = "qcom,sm8150-mmss-noc",
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#define SM8150_MASTER_GPU_TCU 24
|
||||
#define SM8150_MASTER_GRAPHICS_3D 25
|
||||
#define SM8150_MASTER_IPA 26
|
||||
#define SM8150_MASTER_IPA_CORE 27
|
||||
/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
|
||||
#define SM8150_MASTER_LLCC 28
|
||||
#define SM8150_MASTER_MDP_PORT0 29
|
||||
#define SM8150_MASTER_MDP_PORT1 30
|
||||
|
|
@ -94,7 +94,7 @@
|
|||
#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
|
||||
#define SM8150_SLAVE_IMEM_CFG 84
|
||||
#define SM8150_SLAVE_IPA_CFG 85
|
||||
#define SM8150_SLAVE_IPA_CORE 86
|
||||
/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
|
||||
#define SM8150_SLAVE_LLCC 87
|
||||
#define SM8150_SLAVE_LLCC_CFG 88
|
||||
#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89
|
||||
|
|
|
|||
|
|
@ -51,7 +51,6 @@ DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLC
|
|||
DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
|
||||
DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
|
||||
DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
|
||||
DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
|
||||
DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
|
||||
DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
|
||||
|
|
@ -138,7 +137,6 @@ DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_G
|
|||
DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
|
||||
DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
|
||||
DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
|
||||
DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
|
||||
DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
|
||||
DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
|
||||
|
|
@ -171,7 +169,6 @@ DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
|
|||
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
|
||||
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
|
||||
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
|
||||
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
|
||||
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
|
||||
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
|
||||
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
|
||||
|
|
@ -386,22 +383,6 @@ static const struct qcom_icc_desc sm8250_gem_noc = {
|
|||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
|
||||
&bcm_ip0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const ipa_virt_nodes[] = {
|
||||
[MASTER_IPA_CORE] = &ipa_core_master,
|
||||
[SLAVE_IPA_CORE] = &ipa_core_slave,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm8250_ipa_virt = {
|
||||
.nodes = ipa_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
|
||||
.bcms = ipa_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
|
|
@ -531,8 +512,6 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||
.data = &sm8250_dc_noc},
|
||||
{ .compatible = "qcom,sm8250-gem-noc",
|
||||
.data = &sm8250_gem_noc},
|
||||
{ .compatible = "qcom,sm8250-ipa-virt",
|
||||
.data = &sm8250_ipa_virt},
|
||||
{ .compatible = "qcom,sm8250-mc-virt",
|
||||
.data = &sm8250_mc_virt},
|
||||
{ .compatible = "qcom,sm8250-mmss-noc",
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
#define SM8250_MASTER_GPU_TCU 20
|
||||
#define SM8250_MASTER_GRAPHICS_3D 21
|
||||
#define SM8250_MASTER_IPA 22
|
||||
#define SM8250_MASTER_IPA_CORE 23
|
||||
/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
|
||||
#define SM8250_MASTER_LLCC 24
|
||||
#define SM8250_MASTER_MDP_PORT0 25
|
||||
#define SM8250_MASTER_MDP_PORT1 26
|
||||
|
|
@ -92,7 +92,7 @@
|
|||
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
|
||||
#define SM8250_SLAVE_IMEM_CFG 82
|
||||
#define SM8250_SLAVE_IPA_CFG 83
|
||||
#define SM8250_SLAVE_IPA_CORE 84
|
||||
/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
|
||||
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
|
||||
#define SM8250_SLAVE_ISENSE_CFG 86
|
||||
#define SM8250_SLAVE_LLCC 87
|
||||
|
|
|
|||
|
|
@ -108,9 +108,6 @@
|
|||
#define SLAVE_LLCC 11
|
||||
#define SLAVE_SERVICE_GEM_NOC 12
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI1 1
|
||||
|
||||
|
|
|
|||
|
|
@ -129,9 +129,6 @@
|
|||
#define SLAVE_SERVICE_GEM_NOC 16
|
||||
#define SLAVE_SERVICE_GEM_NOC_1 17
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI_CH0 1
|
||||
|
||||
|
|
|
|||
|
|
@ -48,11 +48,11 @@
|
|||
#define SLAVE_SERVICE_A2NOC 19
|
||||
|
||||
/* clk_virt */
|
||||
#define MASTER_IPA_CORE 0
|
||||
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
|
||||
#define MASTER_QUP_CORE_0 1
|
||||
#define MASTER_QUP_CORE_1 2
|
||||
#define MASTER_QUP_CORE_2 3
|
||||
#define SLAVE_IPA_CORE 4
|
||||
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
|
||||
#define SLAVE_QUP_CORE_0 5
|
||||
#define SLAVE_QUP_CORE_1 6
|
||||
#define SLAVE_QUP_CORE_2 7
|
||||
|
|
|
|||
|
|
@ -70,7 +70,5 @@
|
|||
#define SLAVE_QDSS_STM 48
|
||||
#define SLAVE_TCU 49
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -121,9 +121,6 @@
|
|||
#define SLAVE_LLCC 15
|
||||
#define SLAVE_SERVICE_GEM_NOC 16
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI_CH0 1
|
||||
|
||||
|
|
|
|||
|
|
@ -115,9 +115,6 @@
|
|||
#define SLAVE_SERVICE_GEM_NOC_2 15
|
||||
#define SLAVE_SERVICE_GEM_NOC 16
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI_CH0 1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue