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arm64: dts: qcom: use UFS symbol clocks provided by PHY
Remove manually created symbol clocks and replace them with clocks provided by PHY. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221123104443.3415267-5-dmitry.baryshkov@linaro.org
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parent
186b27135a
commit
86543bc6ee
3 changed files with 21 additions and 24 deletions
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@ -720,7 +720,9 @@ gcc: clock-controller@300000 {
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<&pciephy_1>,
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<&pciephy_2>,
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<&ssusb_phy_0>,
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<0>, <0>, <0>;
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<&ufsphy_lane 0>,
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<&ufsphy_lane 1>,
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<&ufsphy_lane 2>;
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clock-names = "cxo",
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"cxo2",
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"sleep_clk",
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@ -2052,6 +2054,7 @@ ufsphy_lane: phy@627400 {
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reg = <0x627400 0x12c>,
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<0x627600 0x200>,
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<0x627c00 0x1b4>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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@ -37,24 +37,6 @@ sleep_clk: sleep-clk {
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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#clock-cells = <0>;
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};
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ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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@ -666,9 +648,9 @@ gcc: clock-controller@100000 {
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<0>,
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<0>,
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<0>,
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<&ufs_phy_rx_symbol_0_clk>,
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<&ufs_phy_rx_symbol_1_clk>,
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<&ufs_phy_tx_symbol_0_clk>,
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<&ufs_mem_phy_lanes 0>,
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<&ufs_mem_phy_lanes 1>,
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<&ufs_mem_phy_lanes 2>,
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<0>,
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<0>;
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};
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@ -2371,6 +2353,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
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<0 0x01d87c00 0 0x200>,
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<0 0x01d87800 0 0x188>,
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<0 0x01d87a00 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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@ -743,11 +743,21 @@ gcc: clock-controller@100000 {
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&pcie0_lane>,
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<&pcie1_lane>;
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<&pcie1_lane>,
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<0>,
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<&ufs_mem_phy_lanes 0>,
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<&ufs_mem_phy_lanes 1>,
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<&ufs_mem_phy_lanes 2>,
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<0>;
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clock-names = "bi_tcxo",
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"sleep_clk",
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"pcie_0_pipe_clk",
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"pcie_1_pipe_clk";
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"pcie_1_pipe_clk",
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"pcie_1_phy_aux_clk",
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"ufs_phy_rx_symbol_0_clk",
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"ufs_phy_rx_symbol_1_clk",
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"ufs_phy_tx_symbol_0_clk",
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"usb3_phy_wrapper_gcc_usb30_pipe_clk";
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};
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gpi_dma2: dma-controller@800000 {
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@ -4049,6 +4059,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
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<0 0x01d87c00 0 0x200>,
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<0 0x01d87800 0 0x188>,
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<0 0x01d87a00 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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