drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.c
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
8c1dcb6573
commit
8663bc7cde
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@ -161,116 +161,6 @@ out:
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return ret;
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}
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static u32
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dp_link_bw_get(struct drm_device *dev, int or, int link)
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{
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u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
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if (!(ctrl & 0x000c0000))
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return 162000;
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return 270000;
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}
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static int
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dp_lane_count_get(struct drm_device *dev, int or, int link)
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{
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u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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switch (ctrl & 0x000f0000) {
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case 0x00010000: return 1;
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case 0x00030000: return 2;
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default:
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return 4;
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}
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}
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void
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nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
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{
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const u32 symbol = 100000;
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int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
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int TU, VTUi, VTUf, VTUa;
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u64 link_data_rate, link_ratio, unk;
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u32 best_diff = 64 * symbol;
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u32 link_nr, link_bw, r;
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/* calculate packed data rate for each lane */
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link_nr = dp_lane_count_get(dev, or, link);
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link_data_rate = (clk * bpp / 8) / link_nr;
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/* calculate ratio of packed data rate to link symbol rate */
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link_bw = dp_link_bw_get(dev, or, link);
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link_ratio = link_data_rate * symbol;
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r = do_div(link_ratio, link_bw);
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for (TU = 64; TU >= 32; TU--) {
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/* calculate average number of valid symbols in each TU */
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u32 tu_valid = link_ratio * TU;
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u32 calc, diff;
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/* find a hw representation for the fraction.. */
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VTUi = tu_valid / symbol;
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calc = VTUi * symbol;
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diff = tu_valid - calc;
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if (diff) {
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if (diff >= (symbol / 2)) {
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VTUf = symbol / (symbol - diff);
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if (symbol - (VTUf * diff))
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VTUf++;
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if (VTUf <= 15) {
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VTUa = 1;
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calc += symbol - (symbol / VTUf);
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} else {
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VTUa = 0;
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VTUf = 1;
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calc += symbol;
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}
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} else {
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VTUa = 0;
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VTUf = min((int)(symbol / diff), 15);
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calc += symbol / VTUf;
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}
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diff = calc - tu_valid;
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} else {
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/* no remainder, but the hw doesn't like the fractional
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* part to be zero. decrement the integer part and
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* have the fraction add a whole symbol back
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*/
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VTUa = 0;
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VTUf = 1;
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VTUi--;
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}
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if (diff < best_diff) {
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best_diff = diff;
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bestTU = TU;
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bestVTUa = VTUa;
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bestVTUf = VTUf;
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bestVTUi = VTUi;
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if (diff == 0)
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break;
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}
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}
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if (!bestTU) {
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NV_ERROR(dev, "DP: unable to find suitable config\n");
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return;
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}
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/* XXX close to vbios numbers, but not right */
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unk = (symbol - link_ratio) * bestTU;
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unk *= link_ratio;
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r = do_div(unk, symbol);
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r = do_div(unk, symbol);
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unk += 6;
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
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nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
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bestVTUf << 16 |
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bestVTUi << 8 |
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unk);
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}
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u8 *
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nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
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{
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@ -318,13 +208,10 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
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* link training
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*****************************************************************************/
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struct dp_state {
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struct dp_train_func *func;
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struct dcb_entry *dcb;
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u8 *table;
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u8 *entry;
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int auxch;
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int crtc;
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int or;
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int link;
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u8 *dpcd;
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int link_nr;
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u32 link_bw;
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@ -335,100 +222,48 @@ struct dp_state {
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static void
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dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
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{
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int or = dp->or, link = dp->link;
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u8 *entry, sink[2];
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u32 dp_ctrl;
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u16 script;
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u8 sink[2];
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NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
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/* set selected link rate on source */
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switch (dp->link_bw) {
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case 270000:
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nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
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sink[0] = DP_LINK_BW_2_7;
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break;
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default:
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nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
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sink[0] = DP_LINK_BW_1_62;
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break;
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}
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/* offset +0x0a of each dp encoder table entry is a pointer to another
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* table, that has (among other things) pointers to more scripts that
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* need to be executed, this time depending on link speed.
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*/
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entry = ROMPTR(dev, dp->entry[10]);
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if (entry) {
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if (dp->table[0] < 0x30) {
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while (dp->link_bw < (ROM16(entry[0]) * 10))
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entry += 4;
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script = ROM16(entry[2]);
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} else {
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while (dp->link_bw < (entry[0] * 27000))
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entry += 3;
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script = ROM16(entry[1]);
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}
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nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
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}
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/* configure lane count on the source */
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dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
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sink[1] = dp->link_nr;
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if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
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dp_ctrl |= 0x00004000;
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sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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}
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
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/* set desired link configuration on the source */
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dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
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dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
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/* inform the sink of the new configuration */
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sink[0] = dp->link_bw / 27000;
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sink[1] = dp->link_nr;
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if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
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sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
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}
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static void
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dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
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dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
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{
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u8 sink_tp;
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NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
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NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);
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nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
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dp->func->train_set(dev, dp->dcb, pattern);
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auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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sink_tp &= ~DP_TRAINING_PATTERN_MASK;
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sink_tp |= tp;
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sink_tp |= pattern;
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auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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}
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static const u8 nv50_lane_map[] = { 16, 8, 0, 24 };
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static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 };
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static int
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dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 mask = 0, drv = 0, pre = 0, unk = 0;
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const u8 *shifts;
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int link = dp->link;
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int or = dp->or;
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int i;
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if (dev_priv->chipset != 0xaf)
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shifts = nv50_lane_map;
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else
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shifts = nvaf_lane_map;
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for (i = 0; i < dp->link_nr; i++) {
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u8 *conf = dp->entry + dp->table[4];
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u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 lpre = (lane & 0x0c) >> 2;
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u8 lvsw = (lane & 0x03) >> 0;
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mask |= 0xff << shifts[i];
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unk |= 1 << (shifts[i] >> 3);
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dp->conf[i] = (lpre << 3) | lvsw;
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if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
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dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
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@ -436,41 +271,9 @@ dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
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dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
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if (dp->table[0] < 0x30) {
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u8 *last = conf + (dp->entry[4] * dp->table[5]);
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while (lvsw != conf[0] || lpre != conf[1]) {
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conf += dp->table[5];
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if (conf >= last)
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return -EINVAL;
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}
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conf += 2;
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} else {
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/* no lookup table anymore, set entries for each
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* combination of voltage swing and pre-emphasis
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* level allowed by the DP spec.
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*/
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switch (lvsw) {
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case 0: lpre += 0; break;
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case 1: lpre += 4; break;
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case 2: lpre += 7; break;
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case 3: lpre += 9; break;
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}
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conf = conf + (lpre * dp->table[5]);
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conf++;
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}
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drv |= conf[0] << shifts[i];
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pre |= conf[1] << shifts[i];
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unk = (unk & ~0x0000ff00) | (conf[2] << 8);
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dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
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}
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nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
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nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
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nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
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return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
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}
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@ -598,7 +401,8 @@ dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
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}
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bool
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nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
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nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
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struct dp_train_func *func)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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@ -614,15 +418,10 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
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if (!auxch)
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return false;
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dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry);
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if (!dp.table)
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return -EINVAL;
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dp.func = func;
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dp.dcb = nv_encoder->dcb;
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dp.crtc = nv_crtc->index;
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dp.auxch = auxch->drive;
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dp.or = nv_encoder->or;
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dp.link = !(nv_encoder->dcb->sorconf.link & 1);
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dp.dpcd = nv_encoder->dp.dpcd;
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/* some sinks toggle hotplug in response to some of the actions
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@ -1162,14 +1162,6 @@ int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
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/* nouveau_hdmi.c */
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void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
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/* nouveau_dp.c */
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int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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uint8_t *data, int data_nr);
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bool nouveau_dp_detect(struct drm_encoder *);
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bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
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void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
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u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
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/* nv04_fb.c */
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extern int nv04_fb_vram_init(struct drm_device *);
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extern int nv04_fb_init(struct drm_device *);
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@ -32,6 +32,14 @@
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#define NV_DPMS_CLEARED 0x80
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struct dp_train_func {
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void (*link_set)(struct drm_device *, struct dcb_entry *, int crtc,
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int nr, u32 bw, bool enhframe);
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void (*train_set)(struct drm_device *, struct dcb_entry *, u8 pattern);
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void (*train_adj)(struct drm_device *, struct dcb_entry *,
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u8 lane, u8 swing, u8 preem);
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};
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struct nouveau_encoder {
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struct drm_encoder_slave base;
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@ -78,9 +86,19 @@ get_slave_funcs(struct drm_encoder *enc)
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return to_encoder_slave(enc)->slave_funcs;
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}
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/* nouveau_dp.c */
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int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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uint8_t *data, int data_nr);
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bool nouveau_dp_detect(struct drm_encoder *);
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bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate,
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struct dp_train_func *);
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u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
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struct nouveau_connector *
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nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
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int nv50_sor_create(struct drm_connector *, struct dcb_entry *);
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void nv50_sor_dp_calc_tu(struct drm_device *, int, int, u32, u32);
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int nv50_dac_create(struct drm_connector *, struct dcb_entry *);
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#endif /* __NOUVEAU_ENCODER_H__ */
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@ -863,9 +863,9 @@ nv50_display_unk20_handler(struct drm_device *dev)
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if (type == OUTPUT_DP) {
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int link = !(dcb->dpconf.sor.link & 1);
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if ((mc & 0x000f0000) == 0x00020000)
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nouveau_dp_tu_update(dev, or, link, pclk, 18);
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nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
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else
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nouveau_dp_tu_update(dev, or, link, pclk, 24);
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nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
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}
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if (dcb->type != OUTPUT_ANALOG) {
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@ -36,6 +36,193 @@
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#include "nouveau_crtc.h"
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#include "nv50_display.h"
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static u32
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nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
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static const u8 nv50[] = { 16, 8, 0, 24 };
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if (dev_priv->card_type == 0xaf)
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return nvaf[lane];
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return nv50[lane];
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}
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static void
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nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
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{
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u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
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}
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static void
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nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
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u8 lane, u8 swing, u8 preem)
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{
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u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
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u32 mask = 0x000000ff << shift;
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u8 *table, *entry, *config;
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table = nouveau_dp_bios_data(dev, dcb, &entry);
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if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
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NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
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return;
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}
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config = entry + table[4];
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while (config[0] != swing || config[1] != preem) {
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config += table[5];
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if (config >= entry + table[4] + entry[4] * table[5])
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||||
return;
|
||||
}
|
||||
|
||||
nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
|
||||
nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
|
||||
nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
|
||||
int link_nr, u32 link_bw, bool enhframe)
|
||||
{
|
||||
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
|
||||
u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
|
||||
u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800)) & ~0x000c0000;
|
||||
u8 *table, *entry, mask;
|
||||
int i;
|
||||
|
||||
table = nouveau_dp_bios_data(dev, dcb, &entry);
|
||||
if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
|
||||
NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
|
||||
return;
|
||||
}
|
||||
|
||||
entry = ROMPTR(dev, entry[10]);
|
||||
if (entry) {
|
||||
while (link_bw < ROM16(entry[0]) * 10)
|
||||
entry += 4;
|
||||
|
||||
nouveau_bios_run_init_table(dev, ROM16(entry[2]), dcb, crtc);
|
||||
}
|
||||
|
||||
dpctrl |= ((1 << link_nr) - 1) << 16;
|
||||
if (enhframe)
|
||||
dpctrl |= 0x00004000;
|
||||
|
||||
if (link_bw > 162000)
|
||||
clksor |= 0x00040000;
|
||||
|
||||
nv_wr32(dev, 0x614300 + (or * 0x800), clksor);
|
||||
nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), dpctrl);
|
||||
|
||||
mask = 0;
|
||||
for (i = 0; i < link_nr; i++)
|
||||
mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
|
||||
nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
|
||||
{
|
||||
u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000;
|
||||
u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800));
|
||||
if (clksor & 0x000c0000)
|
||||
*bw = 270000;
|
||||
else
|
||||
*bw = 162000;
|
||||
|
||||
if (dpctrl > 0x00030000) *nr = 4;
|
||||
else if (dpctrl > 0x00010000) *nr = 2;
|
||||
else *nr = 1;
|
||||
}
|
||||
|
||||
void
|
||||
nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
|
||||
{
|
||||
const u32 symbol = 100000;
|
||||
int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
|
||||
int TU, VTUi, VTUf, VTUa;
|
||||
u64 link_data_rate, link_ratio, unk;
|
||||
u32 best_diff = 64 * symbol;
|
||||
u32 link_nr, link_bw, r;
|
||||
|
||||
/* calculate packed data rate for each lane */
|
||||
nv50_sor_dp_link_get(dev, or, link, &link_nr, &link_bw);
|
||||
link_data_rate = (clk * bpp / 8) / link_nr;
|
||||
|
||||
/* calculate ratio of packed data rate to link symbol rate */
|
||||
link_ratio = link_data_rate * symbol;
|
||||
r = do_div(link_ratio, link_bw);
|
||||
|
||||
for (TU = 64; TU >= 32; TU--) {
|
||||
/* calculate average number of valid symbols in each TU */
|
||||
u32 tu_valid = link_ratio * TU;
|
||||
u32 calc, diff;
|
||||
|
||||
/* find a hw representation for the fraction.. */
|
||||
VTUi = tu_valid / symbol;
|
||||
calc = VTUi * symbol;
|
||||
diff = tu_valid - calc;
|
||||
if (diff) {
|
||||
if (diff >= (symbol / 2)) {
|
||||
VTUf = symbol / (symbol - diff);
|
||||
if (symbol - (VTUf * diff))
|
||||
VTUf++;
|
||||
|
||||
if (VTUf <= 15) {
|
||||
VTUa = 1;
|
||||
calc += symbol - (symbol / VTUf);
|
||||
} else {
|
||||
VTUa = 0;
|
||||
VTUf = 1;
|
||||
calc += symbol;
|
||||
}
|
||||
} else {
|
||||
VTUa = 0;
|
||||
VTUf = min((int)(symbol / diff), 15);
|
||||
calc += symbol / VTUf;
|
||||
}
|
||||
|
||||
diff = calc - tu_valid;
|
||||
} else {
|
||||
/* no remainder, but the hw doesn't like the fractional
|
||||
* part to be zero. decrement the integer part and
|
||||
* have the fraction add a whole symbol back
|
||||
*/
|
||||
VTUa = 0;
|
||||
VTUf = 1;
|
||||
VTUi--;
|
||||
}
|
||||
|
||||
if (diff < best_diff) {
|
||||
best_diff = diff;
|
||||
bestTU = TU;
|
||||
bestVTUa = VTUa;
|
||||
bestVTUf = VTUf;
|
||||
bestVTUi = VTUi;
|
||||
if (diff == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!bestTU) {
|
||||
NV_ERROR(dev, "DP: unable to find suitable config\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* XXX close to vbios numbers, but not right */
|
||||
unk = (symbol - link_ratio) * bestTU;
|
||||
unk *= link_ratio;
|
||||
r = do_div(unk, symbol);
|
||||
r = do_div(unk, symbol);
|
||||
unk += 6;
|
||||
|
||||
nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
|
||||
nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
|
||||
bestVTUf << 16 |
|
||||
bestVTUi << 8 |
|
||||
unk);
|
||||
}
|
||||
static void
|
||||
nv50_sor_disconnect(struct drm_encoder *encoder)
|
||||
{
|
||||
|
|
@ -124,9 +311,16 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
|
|||
return;
|
||||
|
||||
if (mode == DRM_MODE_DPMS_ON) {
|
||||
struct dp_train_func func = {
|
||||
.link_set = nv50_sor_dp_link_set,
|
||||
.train_set = nv50_sor_dp_train_set,
|
||||
.train_adj = nv50_sor_dp_train_adj
|
||||
};
|
||||
u32 rate = nv_encoder->dp.datarate;
|
||||
u8 status = DP_SET_POWER_D0;
|
||||
|
||||
nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
|
||||
nouveau_dp_link_train(encoder, nv_encoder->dp.datarate);
|
||||
nouveau_dp_link_train(encoder, rate, &func);
|
||||
} else {
|
||||
u8 status = DP_SET_POWER_D3;
|
||||
nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
|
||||
|
|
|
|||
Loading…
Reference in New Issue