mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/tglx/linux-2.6-tcc into devel-stable
This commit is contained in:
commit
8688a1a863
387 changed files with 3268 additions and 1564 deletions
1
.gitignore
vendored
1
.gitignore
vendored
|
@ -28,6 +28,7 @@ modules.builtin
|
|||
*.gz
|
||||
*.bz2
|
||||
*.lzma
|
||||
*.xz
|
||||
*.lzo
|
||||
*.patch
|
||||
*.gcno
|
||||
|
|
|
@ -40,8 +40,6 @@ decnet.txt
|
|||
- info on using the DECnet networking layer in Linux.
|
||||
depca.txt
|
||||
- the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
|
||||
dgrs.txt
|
||||
- the Digi International RightSwitch SE-X Ethernet driver
|
||||
dmfe.txt
|
||||
- info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
|
||||
e100.txt
|
||||
|
@ -50,8 +48,6 @@ e1000.txt
|
|||
- info on Intel's E1000 line of gigabit ethernet boards
|
||||
eql.txt
|
||||
- serial IP load balancing
|
||||
ethertap.txt
|
||||
- the Ethertap user space packet reception and transmission driver
|
||||
ewrk3.txt
|
||||
- the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
|
||||
filter.txt
|
||||
|
@ -104,8 +100,6 @@ tuntap.txt
|
|||
- TUN/TAP device driver, allowing user space Rx/Tx of packets.
|
||||
vortex.txt
|
||||
- info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
|
||||
wavelan.txt
|
||||
- AT&T GIS (nee NCR) WaveLAN card: An Ethernet-like radio transceiver
|
||||
x25.txt
|
||||
- general info on X.25 development.
|
||||
x25-iface.txt
|
||||
|
|
|
@ -61,7 +61,6 @@ before the more general line given above as the first match is the one taken.
|
|||
create dns_resolver foo:* * /usr/sbin/dns.foo %k
|
||||
|
||||
|
||||
|
||||
=====
|
||||
USAGE
|
||||
=====
|
||||
|
@ -104,6 +103,14 @@ implemented in the module can be called after doing:
|
|||
returned also.
|
||||
|
||||
|
||||
===============================
|
||||
READING DNS KEYS FROM USERSPACE
|
||||
===============================
|
||||
|
||||
Keys of dns_resolver type can be read from userspace using keyctl_read() or
|
||||
"keyctl read/print/pipe".
|
||||
|
||||
|
||||
=========
|
||||
MECHANISM
|
||||
=========
|
||||
|
|
26
MAINTAINERS
26
MAINTAINERS
|
@ -1010,6 +1010,15 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
|||
S: Maintained
|
||||
F: arch/arm/mach-s5p*/
|
||||
|
||||
ARM/SAMSUNG MOBILE MACHINE SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-s5pv210/mach-aquila.c
|
||||
F: arch/arm/mach-s5pv210/mach-goni.c
|
||||
F: arch/arm/mach-exynos4/mach-universal_c210.c
|
||||
F: arch/arm/mach-exynos4/mach-nuri.c
|
||||
|
||||
ARM/SAMSUNG S5P SERIES FIMC SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
|
@ -1467,6 +1476,7 @@ F: include/net/bluetooth/
|
|||
|
||||
BONDING DRIVER
|
||||
M: Jay Vosburgh <fubar@us.ibm.com>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/bonding/
|
||||
S: Supported
|
||||
|
@ -1692,6 +1702,13 @@ M: Andy Whitcroft <apw@canonical.com>
|
|||
S: Supported
|
||||
F: scripts/checkpatch.pl
|
||||
|
||||
CHINESE DOCUMENTATION
|
||||
M: Harry Wei <harryxiyou@gmail.com>
|
||||
L: xiyoulinuxkernelgroup@googlegroups.com
|
||||
L: linux-kernel@zh-kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/zh_CN/
|
||||
|
||||
CISCO VIC ETHERNET NIC DRIVER
|
||||
M: Vasanthy Kolluri <vkolluri@cisco.com>
|
||||
M: Roopa Prabhu <roprabhu@cisco.com>
|
||||
|
@ -2026,7 +2043,7 @@ F: Documentation/scsi/dc395x.txt
|
|||
F: drivers/scsi/dc395x.*
|
||||
|
||||
DCCP PROTOCOL
|
||||
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
|
||||
M: Gerrit Renker <gerrit@erg.abdn.ac.uk>
|
||||
L: dccp@vger.kernel.org
|
||||
W: http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
|
||||
S: Maintained
|
||||
|
@ -3512,7 +3529,7 @@ F: drivers/hwmon/jc42.c
|
|||
F: Documentation/hwmon/jc42
|
||||
|
||||
JFS FILESYSTEM
|
||||
M: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
|
||||
M: Dave Kleikamp <shaggy@kernel.org>
|
||||
L: jfs-discussion@lists.sourceforge.net
|
||||
W: http://jfs.sourceforge.net/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6.git
|
||||
|
@ -5164,6 +5181,7 @@ F: drivers/char/random.c
|
|||
|
||||
RAPIDIO SUBSYSTEM
|
||||
M: Matt Porter <mporter@kernel.crashing.org>
|
||||
M: Alexandre Bounine <alexandre.bounine@idt.com>
|
||||
S: Maintained
|
||||
F: drivers/rapidio/
|
||||
|
||||
|
@ -5266,7 +5284,7 @@ S: Maintained
|
|||
F: drivers/net/wireless/rtl818x/rtl8180/
|
||||
|
||||
RTL8187 WIRELESS DRIVER
|
||||
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
|
||||
M: Herton Ronaldo Krzesinski <herton@canonical.com>
|
||||
M: Hin-Tak Leung <htl10@users.sourceforge.net>
|
||||
M: Larry Finger <Larry.Finger@lwfinger.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
@ -6104,7 +6122,7 @@ S: Maintained
|
|||
F: security/tomoyo/
|
||||
|
||||
TOPSTAR LAPTOP EXTRAS DRIVER
|
||||
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
|
||||
M: Herton Ronaldo Krzesinski <herton@canonical.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/topstar-laptop.c
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 38
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = Flesh-Eating Bats with Fangs
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -11,6 +11,7 @@ config ALPHA
|
|||
select HAVE_GENERIC_HARDIRQS
|
||||
select GENERIC_IRQ_PROBE
|
||||
select AUTO_IRQ_AFFINITY if SMP
|
||||
select GENERIC_HARDIRQS_NO_DEPRECATED
|
||||
help
|
||||
The Alpha is a 64-bit general-purpose processor designed and
|
||||
marketed by the Digital Equipment Corporation of blessed memory,
|
||||
|
|
|
@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
|
|||
|
||||
int irq_select_affinity(unsigned int irq)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc[irq];
|
||||
struct irq_data *data = irq_get_irq_data(irq);
|
||||
struct irq_chip *chip;
|
||||
static int last_cpu;
|
||||
int cpu = last_cpu + 1;
|
||||
|
||||
if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
|
||||
if (!data)
|
||||
return 1;
|
||||
chip = irq_data_get_irq_chip(data);
|
||||
|
||||
if (!chip->irq_set_affinity || irq_user_affinity[irq])
|
||||
return 1;
|
||||
|
||||
while (!cpu_possible(cpu) ||
|
||||
|
@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
|
|||
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
|
||||
last_cpu = cpu;
|
||||
|
||||
cpumask_copy(desc->affinity, cpumask_of(cpu));
|
||||
get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
|
||||
cpumask_copy(data->affinity, cpumask_of(cpu));
|
||||
chip->irq_set_affinity(data, cpumask_of(cpu), false);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
|
|
@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
|
|||
void __init
|
||||
init_rtc_irq(void)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(RTC_IRQ);
|
||||
|
||||
if (desc) {
|
||||
desc->status |= IRQ_DISABLED;
|
||||
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
handle_simple_irq, "RTC");
|
||||
setup_irq(RTC_IRQ, &timer_irqaction);
|
||||
}
|
||||
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
handle_simple_irq, "RTC");
|
||||
setup_irq(RTC_IRQ, &timer_irqaction);
|
||||
}
|
||||
|
||||
/* Dummy irqactions. */
|
||||
|
|
|
@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
|
|||
}
|
||||
|
||||
inline void
|
||||
i8259a_enable_irq(unsigned int irq)
|
||||
i8259a_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&i8259_irq_lock);
|
||||
i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
|
||||
i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
|
||||
spin_unlock(&i8259_irq_lock);
|
||||
}
|
||||
|
||||
|
@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
void
|
||||
i8259a_disable_irq(unsigned int irq)
|
||||
i8259a_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&i8259_irq_lock);
|
||||
__i8259a_disable_irq(irq);
|
||||
__i8259a_disable_irq(d->irq);
|
||||
spin_unlock(&i8259_irq_lock);
|
||||
}
|
||||
|
||||
void
|
||||
i8259a_mask_and_ack_irq(unsigned int irq)
|
||||
i8259a_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
spin_lock(&i8259_irq_lock);
|
||||
__i8259a_disable_irq(irq);
|
||||
|
||||
|
@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
struct irq_chip i8259a_irq_type = {
|
||||
.name = "XT-PIC",
|
||||
.unmask = i8259a_enable_irq,
|
||||
.mask = i8259a_disable_irq,
|
||||
.mask_ack = i8259a_mask_and_ack_irq,
|
||||
.irq_unmask = i8259a_enable_irq,
|
||||
.irq_mask = i8259a_disable_irq,
|
||||
.irq_mask_ack = i8259a_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
void __init
|
||||
|
|
|
@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
|
|||
|
||||
extern void common_init_isa_dma(void);
|
||||
|
||||
extern void i8259a_enable_irq(unsigned int);
|
||||
extern void i8259a_disable_irq(unsigned int);
|
||||
extern void i8259a_mask_and_ack_irq(unsigned int);
|
||||
extern unsigned int i8259a_startup_irq(unsigned int);
|
||||
extern void i8259a_end_irq(unsigned int);
|
||||
extern void i8259a_enable_irq(struct irq_data *d);
|
||||
extern void i8259a_disable_irq(struct irq_data *d);
|
||||
extern void i8259a_mask_and_ack_irq(struct irq_data *d);
|
||||
extern struct irq_chip i8259a_irq_type;
|
||||
extern void init_i8259a_irqs(void);
|
||||
|
||||
|
|
|
@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
pyxis_enable_irq(unsigned int irq)
|
||||
pyxis_enable_irq(struct irq_data *d)
|
||||
{
|
||||
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
pyxis_disable_irq(unsigned int irq)
|
||||
pyxis_disable_irq(struct irq_data *d)
|
||||
{
|
||||
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static void
|
||||
pyxis_mask_and_ack_irq(unsigned int irq)
|
||||
pyxis_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit = 1UL << (irq - 16);
|
||||
unsigned long bit = 1UL << (d->irq - 16);
|
||||
unsigned long mask = cached_irq_mask &= ~bit;
|
||||
|
||||
/* Disable the interrupt. */
|
||||
|
@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip pyxis_irq_type = {
|
||||
.name = "PYXIS",
|
||||
.mask_ack = pyxis_mask_and_ack_irq,
|
||||
.mask = pyxis_disable_irq,
|
||||
.unmask = pyxis_enable_irq,
|
||||
.irq_mask_ack = pyxis_mask_and_ack_irq,
|
||||
.irq_mask = pyxis_disable_irq,
|
||||
.irq_unmask = pyxis_enable_irq,
|
||||
};
|
||||
|
||||
void
|
||||
|
@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
|
|||
if ((ignore_mask >> i) & 1)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
setup_irq(16+7, &isa_cascade_irqaction);
|
||||
|
|
|
@ -18,27 +18,27 @@
|
|||
DEFINE_SPINLOCK(srm_irq_lock);
|
||||
|
||||
static inline void
|
||||
srm_enable_irq(unsigned int irq)
|
||||
srm_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&srm_irq_lock);
|
||||
cserve_ena(irq - 16);
|
||||
cserve_ena(d->irq - 16);
|
||||
spin_unlock(&srm_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
srm_disable_irq(unsigned int irq)
|
||||
srm_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&srm_irq_lock);
|
||||
cserve_dis(irq - 16);
|
||||
cserve_dis(d->irq - 16);
|
||||
spin_unlock(&srm_irq_lock);
|
||||
}
|
||||
|
||||
/* Handle interrupts from the SRM, assuming no additional weirdness. */
|
||||
static struct irq_chip srm_irq_type = {
|
||||
.name = "SRM",
|
||||
.unmask = srm_enable_irq,
|
||||
.mask = srm_disable_irq,
|
||||
.mask_ack = srm_disable_irq,
|
||||
.irq_unmask = srm_enable_irq,
|
||||
.irq_mask = srm_disable_irq,
|
||||
.irq_mask_ack = srm_disable_irq,
|
||||
};
|
||||
|
||||
void __init
|
||||
|
@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
|
|||
if (i < 64 && ((ignore_mask >> i) & 1))
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
alcor_enable_irq(unsigned int irq)
|
||||
alcor_enable_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_disable_irq(unsigned int irq)
|
||||
alcor_disable_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_mask_and_ack_irq(unsigned int irq)
|
||||
alcor_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_disable_irq(irq);
|
||||
alcor_disable_irq(d);
|
||||
|
||||
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
|
||||
*(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
|
||||
*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
|
||||
*(vuip)GRU_INT_CLEAR = 0; mb();
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_isa_mask_and_ack_irq(unsigned int irq)
|
||||
alcor_isa_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
i8259a_mask_and_ack_irq(irq);
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
|
||||
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
|
||||
*(vuip)GRU_INT_CLEAR = 0x80000000; mb();
|
||||
|
@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip alcor_irq_type = {
|
||||
.name = "ALCOR",
|
||||
.unmask = alcor_enable_irq,
|
||||
.mask = alcor_disable_irq,
|
||||
.mask_ack = alcor_mask_and_ack_irq,
|
||||
.irq_unmask = alcor_enable_irq,
|
||||
.irq_mask = alcor_disable_irq,
|
||||
.irq_mask_ack = alcor_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -126,9 +126,9 @@ alcor_init_irq(void)
|
|||
if (i >= 16+20 && i <= 16+30)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
|
||||
i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
|
||||
|
||||
init_i8259a_irqs();
|
||||
common_init_isa_dma();
|
||||
|
|
|
@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
cabriolet_enable_irq(unsigned int irq)
|
||||
cabriolet_enable_irq(struct irq_data *d)
|
||||
{
|
||||
cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
|
||||
cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
|
||||
}
|
||||
|
||||
static void
|
||||
cabriolet_disable_irq(unsigned int irq)
|
||||
cabriolet_disable_irq(struct irq_data *d)
|
||||
{
|
||||
cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
|
||||
cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
|
||||
}
|
||||
|
||||
static struct irq_chip cabriolet_irq_type = {
|
||||
.name = "CABRIOLET",
|
||||
.unmask = cabriolet_enable_irq,
|
||||
.mask = cabriolet_disable_irq,
|
||||
.mask_ack = cabriolet_disable_irq,
|
||||
.irq_unmask = cabriolet_enable_irq,
|
||||
.irq_mask = cabriolet_disable_irq,
|
||||
.irq_mask_ack = cabriolet_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
|
|||
for (i = 16; i < 35; ++i) {
|
||||
set_irq_chip_and_handler(i, &cabriolet_irq_type,
|
||||
handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
|
|||
}
|
||||
|
||||
static void
|
||||
dp264_enable_irq(unsigned int irq)
|
||||
dp264_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask |= 1UL << irq;
|
||||
cached_irq_mask |= 1UL << d->irq;
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
dp264_disable_irq(unsigned int irq)
|
||||
dp264_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask &= ~(1UL << irq);
|
||||
cached_irq_mask &= ~(1UL << d->irq);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
clipper_enable_irq(unsigned int irq)
|
||||
clipper_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask |= 1UL << (irq - 16);
|
||||
cached_irq_mask |= 1UL << (d->irq - 16);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
clipper_disable_irq(unsigned int irq)
|
||||
clipper_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask &= ~(1UL << (irq - 16));
|
||||
cached_irq_mask &= ~(1UL << (d->irq - 16));
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
|||
}
|
||||
|
||||
static int
|
||||
dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
{
|
||||
dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cpu_set_irq_affinity(irq, *affinity);
|
||||
cpu_set_irq_affinity(d->irq, *affinity);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
|
||||
|
@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
|||
}
|
||||
|
||||
static int
|
||||
clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
{
|
||||
clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cpu_set_irq_affinity(irq - 16, *affinity);
|
||||
cpu_set_irq_affinity(d->irq - 16, *affinity);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
|
||||
|
@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
|||
}
|
||||
|
||||
static struct irq_chip dp264_irq_type = {
|
||||
.name = "DP264",
|
||||
.unmask = dp264_enable_irq,
|
||||
.mask = dp264_disable_irq,
|
||||
.mask_ack = dp264_disable_irq,
|
||||
.set_affinity = dp264_set_affinity,
|
||||
.name = "DP264",
|
||||
.irq_unmask = dp264_enable_irq,
|
||||
.irq_mask = dp264_disable_irq,
|
||||
.irq_mask_ack = dp264_disable_irq,
|
||||
.irq_set_affinity = dp264_set_affinity,
|
||||
};
|
||||
|
||||
static struct irq_chip clipper_irq_type = {
|
||||
.name = "CLIPPER",
|
||||
.unmask = clipper_enable_irq,
|
||||
.mask = clipper_disable_irq,
|
||||
.mask_ack = clipper_disable_irq,
|
||||
.set_affinity = clipper_set_affinity,
|
||||
.name = "CLIPPER",
|
||||
.irq_unmask = clipper_enable_irq,
|
||||
.irq_mask = clipper_disable_irq,
|
||||
.irq_mask_ack = clipper_disable_irq,
|
||||
.irq_set_affinity = clipper_set_affinity,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
|
|||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
eb64p_enable_irq(unsigned int irq)
|
||||
eb64p_enable_irq(struct irq_data *d)
|
||||
{
|
||||
eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
|
||||
eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
|
||||
}
|
||||
|
||||
static void
|
||||
eb64p_disable_irq(unsigned int irq)
|
||||
eb64p_disable_irq(struct irq_data *d)
|
||||
{
|
||||
eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
|
||||
eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
|
||||
}
|
||||
|
||||
static struct irq_chip eb64p_irq_type = {
|
||||
.name = "EB64P",
|
||||
.unmask = eb64p_enable_irq,
|
||||
.mask = eb64p_disable_irq,
|
||||
.mask_ack = eb64p_disable_irq,
|
||||
.irq_unmask = eb64p_enable_irq,
|
||||
.irq_mask = eb64p_disable_irq,
|
||||
.irq_mask_ack = eb64p_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -118,9 +118,9 @@ eb64p_init_irq(void)
|
|||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
|
||||
}
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
setup_irq(16+5, &isa_cascade_irqaction);
|
||||
|
|
|
@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
eiger_enable_irq(unsigned int irq)
|
||||
eiger_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
|
||||
eiger_update_irq_hw(irq, mask);
|
||||
}
|
||||
|
||||
static void
|
||||
eiger_disable_irq(unsigned int irq)
|
||||
eiger_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
|
||||
eiger_update_irq_hw(irq, mask);
|
||||
|
@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip eiger_irq_type = {
|
||||
.name = "EIGER",
|
||||
.unmask = eiger_enable_irq,
|
||||
.mask = eiger_disable_irq,
|
||||
.mask_ack = eiger_disable_irq,
|
||||
.irq_unmask = eiger_enable_irq,
|
||||
.irq_mask = eiger_disable_irq,
|
||||
.irq_mask_ack = eiger_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -136,8 +138,8 @@ eiger_init_irq(void)
|
|||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -63,34 +63,34 @@
|
|||
*/
|
||||
|
||||
static void
|
||||
jensen_local_enable(unsigned int irq)
|
||||
jensen_local_enable(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_enable_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_enable_irq(d);
|
||||
}
|
||||
|
||||
static void
|
||||
jensen_local_disable(unsigned int irq)
|
||||
jensen_local_disable(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_disable_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_disable_irq(d);
|
||||
}
|
||||
|
||||
static void
|
||||
jensen_local_mask_ack(unsigned int irq)
|
||||
jensen_local_mask_ack(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_mask_and_ack_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
}
|
||||
|
||||
static struct irq_chip jensen_local_irq_type = {
|
||||
.name = "LOCAL",
|
||||
.unmask = jensen_local_enable,
|
||||
.mask = jensen_local_disable,
|
||||
.mask_ack = jensen_local_mask_ack,
|
||||
.irq_unmask = jensen_local_enable,
|
||||
.irq_mask = jensen_local_disable,
|
||||
.irq_mask_ack = jensen_local_mask_ack,
|
||||
};
|
||||
|
||||
static void
|
||||
|
|
|
@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
|
|||
}
|
||||
|
||||
static void
|
||||
io7_enable_irq(unsigned int irq)
|
||||
io7_enable_irq(struct irq_data *d)
|
||||
{
|
||||
volatile unsigned long *ctl;
|
||||
unsigned int irq = d->irq;
|
||||
struct io7 *io7;
|
||||
|
||||
ctl = io7_get_irq_ctl(irq, &io7);
|
||||
|
@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
|
|||
__func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
spin_lock(&io7->irq_lock);
|
||||
*ctl |= 1UL << 24;
|
||||
mb();
|
||||
|
@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
io7_disable_irq(unsigned int irq)
|
||||
io7_disable_irq(struct irq_data *d)
|
||||
{
|
||||
volatile unsigned long *ctl;
|
||||
unsigned int irq = d->irq;
|
||||
struct io7 *io7;
|
||||
|
||||
ctl = io7_get_irq_ctl(irq, &io7);
|
||||
|
@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
|
|||
__func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
spin_lock(&io7->irq_lock);
|
||||
*ctl &= ~(1UL << 24);
|
||||
mb();
|
||||
|
@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
marvel_irq_noop(unsigned int irq)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
marvel_irq_noop_return(unsigned int irq)
|
||||
{
|
||||
return 0;
|
||||
marvel_irq_noop(struct irq_data *d)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static struct irq_chip marvel_legacy_irq_type = {
|
||||
.name = "LEGACY",
|
||||
.mask = marvel_irq_noop,
|
||||
.unmask = marvel_irq_noop,
|
||||
.irq_mask = marvel_irq_noop,
|
||||
.irq_unmask = marvel_irq_noop,
|
||||
};
|
||||
|
||||
static struct irq_chip io7_lsi_irq_type = {
|
||||
.name = "LSI",
|
||||
.unmask = io7_enable_irq,
|
||||
.mask = io7_disable_irq,
|
||||
.mask_ack = io7_disable_irq,
|
||||
.irq_unmask = io7_enable_irq,
|
||||
.irq_mask = io7_disable_irq,
|
||||
.irq_mask_ack = io7_disable_irq,
|
||||
};
|
||||
|
||||
static struct irq_chip io7_msi_irq_type = {
|
||||
.name = "MSI",
|
||||
.unmask = io7_enable_irq,
|
||||
.mask = io7_disable_irq,
|
||||
.ack = marvel_irq_noop,
|
||||
.irq_unmask = io7_enable_irq,
|
||||
.irq_mask = io7_disable_irq,
|
||||
.irq_ack = marvel_irq_noop,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
|
|||
|
||||
/* Set up the lsi irqs. */
|
||||
for (i = 0; i < 128; ++i) {
|
||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
/* Disable the implemented irqs in hardware. */
|
||||
|
@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
|
|||
|
||||
/* Set up the msi irqs. */
|
||||
for (i = 128; i < (128 + 512); ++i) {
|
||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; ++i)
|
||||
|
|
|
@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
mikasa_enable_irq(unsigned int irq)
|
||||
mikasa_enable_irq(struct irq_data *d)
|
||||
{
|
||||
mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
|
||||
mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
mikasa_disable_irq(unsigned int irq)
|
||||
mikasa_disable_irq(struct irq_data *d)
|
||||
{
|
||||
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
|
||||
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip mikasa_irq_type = {
|
||||
.name = "MIKASA",
|
||||
.unmask = mikasa_enable_irq,
|
||||
.mask = mikasa_disable_irq,
|
||||
.mask_ack = mikasa_disable_irq,
|
||||
.irq_unmask = mikasa_enable_irq,
|
||||
.irq_mask = mikasa_disable_irq,
|
||||
.irq_mask_ack = mikasa_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -98,8 +98,8 @@ mikasa_init_irq(void)
|
|||
mikasa_update_irq_hw(0);
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
|
|
@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
|
|||
}
|
||||
|
||||
static void
|
||||
noritake_enable_irq(unsigned int irq)
|
||||
noritake_enable_irq(struct irq_data *d)
|
||||
{
|
||||
noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
|
||||
noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
noritake_disable_irq(unsigned int irq)
|
||||
noritake_disable_irq(struct irq_data *d)
|
||||
{
|
||||
noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
|
||||
noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip noritake_irq_type = {
|
||||
.name = "NORITAKE",
|
||||
.unmask = noritake_enable_irq,
|
||||
.mask = noritake_disable_irq,
|
||||
.mask_ack = noritake_disable_irq,
|
||||
.irq_unmask = noritake_enable_irq,
|
||||
.irq_mask = noritake_disable_irq,
|
||||
.irq_mask_ack = noritake_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -127,8 +127,8 @@ noritake_init_irq(void)
|
|||
outw(0, 0x54c);
|
||||
|
||||
for (i = 16; i < 48; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
|
|
@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
|
|||
(((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
|
||||
|
||||
static inline void
|
||||
rawhide_enable_irq(unsigned int irq)
|
||||
rawhide_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
|
@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
rawhide_disable_irq(unsigned int irq)
|
||||
rawhide_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
|
@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
rawhide_mask_and_ack_irq(unsigned int irq)
|
||||
rawhide_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, mask1, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
|
@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip rawhide_irq_type = {
|
||||
.name = "RAWHIDE",
|
||||
.unmask = rawhide_enable_irq,
|
||||
.mask = rawhide_disable_irq,
|
||||
.mask_ack = rawhide_mask_and_ack_irq,
|
||||
.irq_unmask = rawhide_enable_irq,
|
||||
.irq_mask = rawhide_disable_irq,
|
||||
.irq_mask_ack = rawhide_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -177,8 +180,8 @@ rawhide_init_irq(void)
|
|||
}
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
|
|
@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
rx164_enable_irq(unsigned int irq)
|
||||
rx164_enable_irq(struct irq_data *d)
|
||||
{
|
||||
rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
rx164_disable_irq(unsigned int irq)
|
||||
rx164_disable_irq(struct irq_data *d)
|
||||
{
|
||||
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip rx164_irq_type = {
|
||||
.name = "RX164",
|
||||
.unmask = rx164_enable_irq,
|
||||
.mask = rx164_disable_irq,
|
||||
.mask_ack = rx164_disable_irq,
|
||||
.irq_unmask = rx164_enable_irq,
|
||||
.irq_mask = rx164_disable_irq,
|
||||
.irq_mask_ack = rx164_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -99,8 +99,8 @@ rx164_init_irq(void)
|
|||
|
||||
rx164_update_irq_hw(0);
|
||||
for (i = 16; i < 40; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
|
|
@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
|
|||
/* GENERIC irq routines */
|
||||
|
||||
static inline void
|
||||
sable_lynx_enable_irq(unsigned int irq)
|
||||
sable_lynx_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
|
@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
sable_lynx_disable_irq(unsigned int irq)
|
||||
sable_lynx_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
|
@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
sable_lynx_mask_and_ack_irq(unsigned int irq)
|
||||
sable_lynx_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
|
@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip sable_lynx_irq_type = {
|
||||
.name = "SABLE/LYNX",
|
||||
.unmask = sable_lynx_enable_irq,
|
||||
.mask = sable_lynx_disable_irq,
|
||||
.mask_ack = sable_lynx_mask_and_ack_irq,
|
||||
.irq_unmask = sable_lynx_enable_irq,
|
||||
.irq_mask = sable_lynx_disable_irq,
|
||||
.irq_mask_ack = sable_lynx_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
|
|||
long i;
|
||||
|
||||
for (i = 0; i < nr_of_irqs; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
|
|
|
@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
takara_enable_irq(unsigned int irq)
|
||||
takara_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
|
||||
takara_update_irq_hw(irq, mask);
|
||||
}
|
||||
|
||||
static void
|
||||
takara_disable_irq(unsigned int irq)
|
||||
takara_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
|
||||
takara_update_irq_hw(irq, mask);
|
||||
|
@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip takara_irq_type = {
|
||||
.name = "TAKARA",
|
||||
.unmask = takara_enable_irq,
|
||||
.mask = takara_disable_irq,
|
||||
.mask_ack = takara_disable_irq,
|
||||
.irq_unmask = takara_enable_irq,
|
||||
.irq_mask = takara_disable_irq,
|
||||
.irq_mask_ack = takara_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -136,8 +138,8 @@ takara_init_irq(void)
|
|||
takara_update_irq_hw(i, -1);
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
|
|
|
@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
|
|||
}
|
||||
|
||||
static inline void
|
||||
titan_enable_irq(unsigned int irq)
|
||||
titan_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cached_irq_mask |= 1UL << (irq - 16);
|
||||
titan_update_irq_hw(titan_cached_irq_mask);
|
||||
|
@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static inline void
|
||||
titan_disable_irq(unsigned int irq)
|
||||
titan_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cached_irq_mask &= ~(1UL << (irq - 16));
|
||||
titan_update_irq_hw(titan_cached_irq_mask);
|
||||
|
@ -144,7 +146,8 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
|||
}
|
||||
|
||||
static int
|
||||
titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cpu_set_irq_affinity(irq - 16, *affinity);
|
||||
|
@ -175,17 +178,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
|
|||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip titan_irq_type = {
|
||||
.name = "TITAN",
|
||||
.unmask = titan_enable_irq,
|
||||
.mask = titan_disable_irq,
|
||||
.mask_ack = titan_disable_irq,
|
||||
.set_affinity = titan_set_irq_affinity,
|
||||
.name = "TITAN",
|
||||
.irq_unmask = titan_enable_irq,
|
||||
.irq_mask = titan_disable_irq,
|
||||
.irq_mask_ack = titan_disable_irq,
|
||||
.irq_set_affinity = titan_set_irq_affinity,
|
||||
};
|
||||
|
||||
static irqreturn_t
|
||||
|
|
|
@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
|
|||
}
|
||||
|
||||
static void
|
||||
wildfire_enable_irq(unsigned int irq)
|
||||
wildfire_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_enable_irq(irq);
|
||||
i8259a_enable_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
set_bit(irq, &cached_irq_mask);
|
||||
|
@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
wildfire_disable_irq(unsigned int irq)
|
||||
wildfire_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_disable_irq(irq);
|
||||
i8259a_disable_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
clear_bit(irq, &cached_irq_mask);
|
||||
|
@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
|
|||
}
|
||||
|
||||
static void
|
||||
wildfire_mask_and_ack_irq(unsigned int irq)
|
||||
wildfire_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_mask_and_ack_irq(irq);
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
clear_bit(irq, &cached_irq_mask);
|
||||
|
@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
|
|||
|
||||
static struct irq_chip wildfire_irq_type = {
|
||||
.name = "WILDFIRE",
|
||||
.unmask = wildfire_enable_irq,
|
||||
.mask = wildfire_disable_irq,
|
||||
.mask_ack = wildfire_mask_and_ack_irq,
|
||||
.irq_unmask = wildfire_enable_irq,
|
||||
.irq_mask = wildfire_disable_irq,
|
||||
.irq_mask_ack = wildfire_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void __init
|
||||
|
@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
|
|||
for (i = 0; i < 16; ++i) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
|
||||
for (i = 40; i < 64; ++i) {
|
||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
setup_irq(32+irq_bias, &isa_enable);
|
||||
setup_irq(32+irq_bias, &isa_enable);
|
||||
}
|
||||
|
||||
static void __init
|
||||
|
|
|
@ -6,6 +6,8 @@ config ARM_VIC
|
|||
|
||||
config ARM_VIC_NR
|
||||
int
|
||||
default 4 if ARCH_S5PV210
|
||||
default 3 if ARCH_S5P6442 || ARCH_S5PC100
|
||||
default 2
|
||||
depends on ARM_VIC
|
||||
help
|
||||
|
|
|
@ -15,10 +15,6 @@ struct meminfo;
|
|||
struct sys_timer;
|
||||
|
||||
struct machine_desc {
|
||||
/*
|
||||
* Note! The first two elements are used
|
||||
* by assembler code in head.S, head-common.S
|
||||
*/
|
||||
unsigned int nr; /* architecture number */
|
||||
const char *name; /* architecture name */
|
||||
unsigned long boot_params; /* tagged list */
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#ifndef _ASMARM_PGALLOC_H
|
||||
#define _ASMARM_PGALLOC_H
|
||||
|
||||
#include <linux/pagemap.h>
|
||||
|
||||
#include <asm/domain.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/processor.h>
|
||||
|
|
|
@ -836,9 +836,11 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
|
|||
/*
|
||||
* One-time initialisation.
|
||||
*/
|
||||
static void reset_ctrl_regs(void *unused)
|
||||
static void reset_ctrl_regs(void *info)
|
||||
{
|
||||
int i;
|
||||
int i, cpu = smp_processor_id();
|
||||
u32 dbg_power;
|
||||
cpumask_t *cpumask = info;
|
||||
|
||||
/*
|
||||
* v7 debug contains save and restore registers so that debug state
|
||||
|
@ -849,6 +851,17 @@ static void reset_ctrl_regs(void *unused)
|
|||
* later on.
|
||||
*/
|
||||
if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
|
||||
/*
|
||||
* Ensure sticky power-down is clear (i.e. debug logic is
|
||||
* powered up).
|
||||
*/
|
||||
asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
|
||||
if ((dbg_power & 0x1) == 0) {
|
||||
pr_warning("CPU %d debug is powered down!\n", cpu);
|
||||
cpumask_or(cpumask, cpumask, cpumask_of(cpu));
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Unconditionally clear the lock by writing a value
|
||||
* other than 0xC5ACCE55 to the access register.
|
||||
|
@ -887,6 +900,7 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
|
|||
static int __init arch_hw_breakpoint_init(void)
|
||||
{
|
||||
u32 dscr;
|
||||
cpumask_t cpumask = { CPU_BITS_NONE };
|
||||
|
||||
debug_arch = get_debug_arch();
|
||||
|
||||
|
@ -911,7 +925,13 @@ static int __init arch_hw_breakpoint_init(void)
|
|||
* Reset the breakpoint resources. We assume that a halting
|
||||
* debugger will leave the world in a nice state for us.
|
||||
*/
|
||||
on_each_cpu(reset_ctrl_regs, NULL, 1);
|
||||
on_each_cpu(reset_ctrl_regs, &cpumask, 1);
|
||||
if (!cpumask_empty(&cpumask)) {
|
||||
core_num_brps = 0;
|
||||
core_num_reserved_brps = 0;
|
||||
core_num_wrps = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ARM_DBG_READ(c1, 0, dscr);
|
||||
if (dscr & ARM_DSCR_HDBGEN) {
|
||||
|
|
|
@ -996,10 +996,10 @@ static int ptrace_gethbpregs(struct task_struct *tsk, long num,
|
|||
while (!(arch_ctrl.len & 0x1))
|
||||
arch_ctrl.len >>= 1;
|
||||
|
||||
if (idx & 0x1)
|
||||
reg = encode_ctrl_reg(arch_ctrl);
|
||||
else
|
||||
if (num & 0x1)
|
||||
reg = bp->attr.bp_addr;
|
||||
else
|
||||
reg = encode_ctrl_reg(arch_ctrl);
|
||||
}
|
||||
|
||||
put:
|
||||
|
|
|
@ -132,7 +132,7 @@ static int davinci_target(struct cpufreq_policy *policy,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int __init davinci_cpu_init(struct cpufreq_policy *policy)
|
||||
static int davinci_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int result = 0;
|
||||
struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
|
||||
|
|
|
@ -480,8 +480,15 @@ static struct platform_device da850_mcasp_device = {
|
|||
.resource = da850_mcasp_resources,
|
||||
};
|
||||
|
||||
struct platform_device davinci_pcm_device = {
|
||||
.name = "davinci-pcm-audio",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
|
||||
{
|
||||
platform_device_register(&davinci_pcm_device);
|
||||
|
||||
/* DA830/OMAP-L137 has 3 instances of McASP */
|
||||
if (cpu_is_davinci_da830() && id == 1) {
|
||||
da830_mcasp1_device.dev.platform_data = pdata;
|
||||
|
|
|
@ -58,7 +58,7 @@ static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
spin_lock_irqsave(&ctlr->lock, flags);
|
||||
|
||||
gpio_reg_set_bit(®s->enable, gpio);
|
||||
gpio_reg_set_bit(regs->enable, gpio);
|
||||
|
||||
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||||
|
||||
|
@ -74,7 +74,7 @@ static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
spin_lock_irqsave(&ctlr->lock, flags);
|
||||
|
||||
gpio_reg_clear_bit(®s->enable, gpio);
|
||||
gpio_reg_clear_bit(regs->enable, gpio);
|
||||
|
||||
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||||
}
|
||||
|
@ -88,7 +88,7 @@ static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
spin_lock_irqsave(&ctlr->lock, flags);
|
||||
|
||||
gpio_reg_set_bit(®s->direction, gpio);
|
||||
gpio_reg_set_bit(regs->direction, gpio);
|
||||
|
||||
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||||
|
||||
|
@ -106,11 +106,11 @@ static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
|
|||
spin_lock_irqsave(&ctlr->lock, flags);
|
||||
|
||||
if (value)
|
||||
gpio_reg_set_bit(®s->data_out, gpio);
|
||||
gpio_reg_set_bit(regs->data_out, gpio);
|
||||
else
|
||||
gpio_reg_clear_bit(®s->data_out, gpio);
|
||||
gpio_reg_clear_bit(regs->data_out, gpio);
|
||||
|
||||
gpio_reg_clear_bit(®s->direction, gpio);
|
||||
gpio_reg_clear_bit(regs->direction, gpio);
|
||||
|
||||
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||||
|
||||
|
@ -124,7 +124,7 @@ static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|||
unsigned gpio = chip->base + offset;
|
||||
int ret;
|
||||
|
||||
ret = gpio_reg_get_bit(®s->data_in, gpio);
|
||||
ret = gpio_reg_get_bit(regs->data_in, gpio);
|
||||
|
||||
return ret ? 1 : 0;
|
||||
}
|
||||
|
@ -140,9 +140,9 @@ static void tnetv107x_gpio_set(struct gpio_chip *chip,
|
|||
spin_lock_irqsave(&ctlr->lock, flags);
|
||||
|
||||
if (value)
|
||||
gpio_reg_set_bit(®s->data_out, gpio);
|
||||
gpio_reg_set_bit(regs->data_out, gpio);
|
||||
else
|
||||
gpio_reg_clear_bit(®s->data_out, gpio);
|
||||
gpio_reg_clear_bit(regs->data_out, gpio);
|
||||
|
||||
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||||
}
|
||||
|
|
|
@ -1,6 +1,8 @@
|
|||
#ifndef __MACH_CLKDEV_H
|
||||
#define __MACH_CLKDEV_H
|
||||
|
||||
struct clk;
|
||||
|
||||
static inline int __clk_get(struct clk *clk)
|
||||
{
|
||||
return 1;
|
||||
|
|
|
@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
|
|||
dd = clk->dpll_data;
|
||||
|
||||
/* DPLL divider must result in a valid jitter correction val */
|
||||
fint = clk->parent->rate / (n + 1);
|
||||
fint = clk->parent->rate / n;
|
||||
if (fint < DPLL_FINT_BAND1_MIN) {
|
||||
|
||||
pr_debug("rejecting n=%d due to Fint failure, "
|
||||
|
|
|
@ -193,10 +193,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
|
|||
omap_mbox_type_t irq)
|
||||
{
|
||||
struct omap_mbox2_priv *p = mbox->priv;
|
||||
u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
|
||||
l = mbox_read_reg(p->irqdisable);
|
||||
l &= ~bit;
|
||||
mbox_write_reg(l, p->irqdisable);
|
||||
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
|
||||
|
||||
if (!cpu_is_omap44xx())
|
||||
bit = mbox_read_reg(p->irqdisable) & ~bit;
|
||||
|
||||
mbox_write_reg(bit, p->irqdisable);
|
||||
}
|
||||
|
||||
static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
|
||||
|
@ -334,7 +336,7 @@ static struct omap_mbox mbox_iva_info = {
|
|||
.priv = &omap2_mbox_iva_priv,
|
||||
};
|
||||
|
||||
struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
|
||||
struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4)
|
||||
|
|
|
@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
|
|||
list_for_each_entry(e, &partition->muxmodes, node) {
|
||||
struct omap_mux *m = &e->mux;
|
||||
|
||||
(void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
|
||||
(void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
|
||||
m, &omap_mux_dbg_signal_fops);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
|
|||
|
||||
}
|
||||
|
||||
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
|
||||
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
|
||||
&enable_off_mode, &pm_dbg_option_fops);
|
||||
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
|
||||
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
|
||||
&sleep_while_idle, &pm_dbg_option_fops);
|
||||
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
|
||||
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
|
||||
&wakeup_timer_seconds, &pm_dbg_option_fops);
|
||||
(void) debugfs_create_file("wakeup_timer_milliseconds",
|
||||
S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
|
||||
S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
|
||||
&pm_dbg_option_fops);
|
||||
pm_dbg_init_done = 1;
|
||||
|
||||
|
|
|
@ -38,8 +38,8 @@
|
|||
#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
|
||||
|
||||
/* PRCM_MPU clockdomain register offsets (from instance start) */
|
||||
#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000
|
||||
#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000
|
||||
#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018
|
||||
#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
@ -282,6 +282,7 @@ static int sr_late_init(struct omap_sr *sr_info)
|
|||
dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
|
||||
"interrupt handler. Smartreflex will"
|
||||
"not function as desired\n", __func__);
|
||||
kfree(name);
|
||||
kfree(sr_info);
|
||||
return ret;
|
||||
}
|
||||
|
@ -879,7 +880,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
|||
ret = sr_late_init(sr_info);
|
||||
if (ret) {
|
||||
pr_warning("%s: Error in SR late init\n", __func__);
|
||||
return ret;
|
||||
goto err_release_region;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -890,17 +891,20 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
|||
* not try to create rest of the debugfs entries.
|
||||
*/
|
||||
vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
|
||||
if (!vdd_dbg_dir)
|
||||
return -EINVAL;
|
||||
if (!vdd_dbg_dir) {
|
||||
ret = -EINVAL;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
|
||||
if (IS_ERR(dbg_dir)) {
|
||||
dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
|
||||
__func__);
|
||||
return PTR_ERR(dbg_dir);
|
||||
ret = PTR_ERR(dbg_dir);
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
|
||||
(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
|
||||
(void *)sr_info, &pm_sr_fops);
|
||||
(void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
|
||||
&sr_info->err_weight);
|
||||
|
@ -913,7 +917,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(nvalue_dir)) {
|
||||
dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
|
||||
"for n-values\n", __func__);
|
||||
return PTR_ERR(nvalue_dir);
|
||||
ret = PTR_ERR(nvalue_dir);
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
|
||||
|
@ -922,24 +927,16 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
|||
" corresponding vdd vdd_%s. Cannot create debugfs"
|
||||
"entries for n-values\n",
|
||||
__func__, sr_info->voltdm->name);
|
||||
return -ENODATA;
|
||||
ret = -ENODATA;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
for (i = 0; i < sr_info->nvalue_count; i++) {
|
||||
char *name;
|
||||
char volt_name[32];
|
||||
char name[NVALUE_NAME_LEN + 1];
|
||||
|
||||
name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
|
||||
if (!name) {
|
||||
dev_err(&pdev->dev, "%s: Unable to allocate memory"
|
||||
" for n-value directory name\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
strcpy(name, "volt_");
|
||||
sprintf(volt_name, "%d", volt_data[i].volt_nominal);
|
||||
strcat(name, volt_name);
|
||||
(void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
|
||||
snprintf(name, sizeof(name), "volt_%d",
|
||||
volt_data[i].volt_nominal);
|
||||
(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
|
||||
&(sr_info->nvalue_table[i].nvalue));
|
||||
}
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <asm/mach/time.h>
|
||||
#include <plat/dmtimer.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
#include "timer-gp.h"
|
||||
|
||||
|
@ -190,6 +191,7 @@ static void __init omap2_gp_clocksource_init(void)
|
|||
/*
|
||||
* clocksource
|
||||
*/
|
||||
static DEFINE_CLOCK_DATA(cd);
|
||||
static struct omap_dm_timer *gpt_clocksource;
|
||||
static cycle_t clocksource_read_cycles(struct clocksource *cs)
|
||||
{
|
||||
|
@ -204,6 +206,15 @@ static struct clocksource clocksource_gpt = {
|
|||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static void notrace dmtimer_update_sched_clock(void)
|
||||
{
|
||||
u32 cyc;
|
||||
|
||||
cyc = omap_dm_timer_read_counter(gpt_clocksource);
|
||||
|
||||
update_sched_clock(&cd, cyc, (u32)~0);
|
||||
}
|
||||
|
||||
/* Setup free-running counter for clocksource */
|
||||
static void __init omap2_gp_clocksource_init(void)
|
||||
{
|
||||
|
@ -224,6 +235,8 @@ static void __init omap2_gp_clocksource_init(void)
|
|||
|
||||
omap_dm_timer_set_load_start(gpt, 1, 0);
|
||||
|
||||
init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
|
||||
|
||||
if (clocksource_register_hz(&clocksource_gpt, tick_rate))
|
||||
printk(err2, clocksource_gpt.name);
|
||||
}
|
||||
|
|
|
@ -347,6 +347,7 @@ static struct platform_device *pxa25x_devices[] __initdata = {
|
|||
&pxa25x_device_assp,
|
||||
&pxa25x_device_pwm0,
|
||||
&pxa25x_device_pwm1,
|
||||
&pxa_device_asoc_platform,
|
||||
};
|
||||
|
||||
static struct sys_device pxa25x_sysdev[] = {
|
||||
|
|
|
@ -81,8 +81,6 @@ static int tosa_bt_probe(struct platform_device *dev)
|
|||
goto err_rfk_alloc;
|
||||
}
|
||||
|
||||
rfkill_set_led_trigger_name(rfk, "tosa-bt");
|
||||
|
||||
rc = rfkill_register(rfk);
|
||||
if (rc)
|
||||
goto err_rfkill;
|
||||
|
|
|
@ -875,6 +875,11 @@ static struct platform_device sharpsl_rom_device = {
|
|||
.dev.platform_data = &sharpsl_rom_data,
|
||||
};
|
||||
|
||||
static struct platform_device wm9712_device = {
|
||||
.name = "wm9712-codec",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&tosascoop_device,
|
||||
&tosascoop_jc_device,
|
||||
|
@ -885,6 +890,7 @@ static struct platform_device *devices[] __initdata = {
|
|||
&tosaled_device,
|
||||
&tosa_bt_device,
|
||||
&sharpsl_rom_device,
|
||||
&wm9712_device,
|
||||
};
|
||||
|
||||
static void tosa_poweroff(void)
|
||||
|
|
|
@ -99,6 +99,7 @@ config MACH_NEO1973_GTA02
|
|||
select POWER_SUPPLY
|
||||
select MACH_NEO1973
|
||||
select S3C2410_PWM
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
|
||||
|
||||
|
|
|
@ -44,19 +44,19 @@
|
|||
#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
|
||||
#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
|
||||
|
||||
#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */
|
||||
#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2
|
||||
#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4
|
||||
#define GTA02_GPIO_3D_RESET S3C2440_GPJ5
|
||||
#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */
|
||||
#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7
|
||||
#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8
|
||||
#define GTA02_GPIO_KEEPACT S3C2440_GPJ8
|
||||
#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10
|
||||
#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
|
||||
#define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2)
|
||||
#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4)
|
||||
#define GTA02_GPIO_3D_RESET S3C2410_GPJ(5)
|
||||
#define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */
|
||||
#define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7)
|
||||
#define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8)
|
||||
#define GTA02_GPIO_KEEPACT S3C2410_GPJ(8)
|
||||
#define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10)
|
||||
#define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */
|
||||
#define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */
|
||||
|
||||
#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
|
||||
#define GTA02_IRQ_MODEM IRQ_EINT1
|
||||
|
|
|
@ -150,6 +150,12 @@ static struct clk init_clocks_off[] = {
|
|||
.parent = &clk_p,
|
||||
.enable = s3c64xx_pclk_ctrl,
|
||||
.ctrlbit = S3C_CLKCON_PCLK_IIC,
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 1,
|
||||
.parent = &clk_p,
|
||||
.enable = s3c64xx_pclk_ctrl,
|
||||
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 0,
|
||||
|
|
|
@ -690,12 +690,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
|
|||
|
||||
regptr = regs + PL080_Cx_BASE(0);
|
||||
|
||||
for (ch = 0; ch < 8; ch++, chno++, chptr++) {
|
||||
printk(KERN_INFO "%s: registering DMA %d (%p)\n",
|
||||
__func__, chno, regptr);
|
||||
for (ch = 0; ch < 8; ch++, chptr++) {
|
||||
pr_debug("%s: registering DMA %d (%p)\n",
|
||||
__func__, chno + ch, regptr);
|
||||
|
||||
chptr->bit = 1 << ch;
|
||||
chptr->number = chno;
|
||||
chptr->number = chno + ch;
|
||||
chptr->dmac = dmac;
|
||||
chptr->regs = regptr;
|
||||
regptr += PL080_Cx_STRIDE;
|
||||
|
@ -704,7 +704,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
|
|||
/* for the moment, permanently enable the controller */
|
||||
writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
|
||||
|
||||
printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
|
||||
printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
|
||||
irq, regs, chno, chno+8);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -72,7 +72,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
|
|||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
|
||||
static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
|
||||
}
|
||||
|
@ -138,7 +138,7 @@ static struct s3c_gpio_chip gpio_4bit[] = {
|
|||
},
|
||||
};
|
||||
|
||||
int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
|
||||
static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
||||
#include <linux/mfd/wm8350/core.h>
|
||||
|
@ -351,7 +352,7 @@ static struct regulator_init_data smdk6410_vddpll = {
|
|||
/* VDD_UH_MMC, LDO5 on J5 */
|
||||
static struct regulator_init_data smdk6410_vdduh_mmc = {
|
||||
.constraints = {
|
||||
.name = "PVDD_UH/PVDD_MMC",
|
||||
.name = "PVDD_UH+PVDD_MMC",
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
@ -417,7 +418,7 @@ static struct regulator_init_data smdk6410_vddaudio = {
|
|||
/* S3C64xx internal logic & PLL */
|
||||
static struct regulator_init_data wm8350_dcdc1_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_INT/PVDD_PLL",
|
||||
.name = "PVDD_INT+PVDD_PLL",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.always_on = 1,
|
||||
|
@ -452,7 +453,7 @@ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
|
|||
|
||||
static struct regulator_init_data wm8350_dcdc4_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
|
||||
.name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV",
|
||||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.always_on = 1,
|
||||
|
@ -464,7 +465,7 @@ static struct regulator_init_data wm8350_dcdc4_data = {
|
|||
/* OTGi/1190-EV1 HPVDD & AVDD */
|
||||
static struct regulator_init_data wm8350_ldo4_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_OTGI/HPVDD/AVDD",
|
||||
.name = "PVDD_OTGI+HPVDD+AVDD",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
|
@ -552,7 +553,7 @@ static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
|
|||
|
||||
static struct regulator_init_data wm1192_dcdc3 = {
|
||||
.constraints = {
|
||||
.name = "PVDD_MEM/PVDD_GPS",
|
||||
.name = "PVDD_MEM+PVDD_GPS",
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
@ -563,7 +564,7 @@ static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
|
|||
|
||||
static struct regulator_init_data wm1192_ldo1 = {
|
||||
.constraints = {
|
||||
.name = "PVDD_LCD/PVDD_EXT",
|
||||
.name = "PVDD_LCD+PVDD_EXT",
|
||||
.always_on = 1,
|
||||
},
|
||||
.consumer_supplies = wm1192_ldo1_consumers,
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
||||
{
|
||||
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3));
|
||||
|
||||
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
|
||||
|
|
|
@ -56,7 +56,7 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
|
|||
else
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
|
||||
|
||||
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
|
||||
pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
|
||||
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
|
||||
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
|
||||
}
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
#define S5P6440_GPIO_A_NR (6)
|
||||
#define S5P6440_GPIO_B_NR (7)
|
||||
#define S5P6440_GPIO_C_NR (8)
|
||||
#define S5P6440_GPIO_F_NR (2)
|
||||
#define S5P6440_GPIO_F_NR (16)
|
||||
#define S5P6440_GPIO_G_NR (7)
|
||||
#define S5P6440_GPIO_H_NR (10)
|
||||
#define S5P6440_GPIO_I_NR (16)
|
||||
|
@ -36,7 +36,7 @@
|
|||
#define S5P6450_GPIO_B_NR (7)
|
||||
#define S5P6450_GPIO_C_NR (8)
|
||||
#define S5P6450_GPIO_D_NR (8)
|
||||
#define S5P6450_GPIO_F_NR (2)
|
||||
#define S5P6450_GPIO_F_NR (16)
|
||||
#define S5P6450_GPIO_G_NR (14)
|
||||
#define S5P6450_GPIO_H_NR (10)
|
||||
#define S5P6450_GPIO_I_NR (16)
|
||||
|
|
|
@ -454,6 +454,7 @@ static void __init ag5evm_init(void)
|
|||
gpio_direction_output(GPIO_PORT217, 0);
|
||||
mdelay(1);
|
||||
gpio_set_value(GPIO_PORT217, 1);
|
||||
mdelay(100);
|
||||
|
||||
/* LCD backlight controller */
|
||||
gpio_request(GPIO_PORT235, NULL); /* RESET */
|
||||
|
|
|
@ -1303,7 +1303,7 @@ static void __init ap4evb_init(void)
|
|||
|
||||
lcdc_info.clock_source = LCDC_CLK_BUS;
|
||||
lcdc_info.ch[0].interface_type = RGB18;
|
||||
lcdc_info.ch[0].clock_divider = 2;
|
||||
lcdc_info.ch[0].clock_divider = 3;
|
||||
lcdc_info.ch[0].flags = 0;
|
||||
lcdc_info.ch[0].lcd_size_cfg.width = 152;
|
||||
lcdc_info.ch[0].lcd_size_cfg.height = 91;
|
||||
|
|
|
@ -303,7 +303,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
|
|||
.lcd_cfg = mackerel_lcdc_modes,
|
||||
.num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
|
||||
.interface_type = RGB24,
|
||||
.clock_divider = 2,
|
||||
.clock_divider = 3,
|
||||
.flags = 0,
|
||||
.lcd_size_cfg.width = 152,
|
||||
.lcd_size_cfg.height = 91,
|
||||
|
|
|
@ -263,7 +263,7 @@ static struct clk div6_clks[DIV6_NR] = {
|
|||
};
|
||||
|
||||
enum { MSTP001,
|
||||
MSTP125, MSTP118, MSTP116, MSTP100,
|
||||
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
|
||||
MSTP219,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
|
||||
|
@ -275,6 +275,10 @@ enum { MSTP001,
|
|||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
|
||||
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
|
||||
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
|
||||
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
|
||||
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
|
||||
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
|
||||
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
|
@ -306,6 +310,9 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
|
||||
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
|
||||
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
|
||||
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
|
||||
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
|
||||
CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
|
||||
|
@ -313,11 +320,15 @@ static struct clk_lookup lookups[] = {
|
|||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
|
||||
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
|
||||
CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
|
||||
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
|
||||
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
|
||||
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
|
|
|
@ -6,13 +6,10 @@ LIST "RWT Setting"
|
|||
EW 0xE6020004, 0xA500
|
||||
EW 0xE6030004, 0xA500
|
||||
|
||||
DD 0x01001000, 0x01001000
|
||||
|
||||
LIST "GPIO Setting"
|
||||
EB 0xE6051013, 0xA2
|
||||
|
||||
LIST "CPG"
|
||||
ED 0xE6150080, 0x00000180
|
||||
ED 0xE61500C0, 0x00000002
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
|
|||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
LIST "SUB/USBClk"
|
||||
ED 0xE6150080, 0x00000180
|
||||
|
||||
LIST "BSC"
|
||||
ED 0xFEC10000, 0x00E0001B
|
||||
|
||||
|
@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
|
|||
ED 0xFE40004C, 0x00110209
|
||||
ED 0xFE400010, 0x00000087
|
||||
|
||||
WAIT 10, 0xFE40009C
|
||||
WAIT 30, 0xFE40009C
|
||||
|
||||
ED 0xFE400084, 0x0000003F
|
||||
EB 0xFE500000, 0x00
|
||||
|
@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
|
|||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xE6150354, 0x00000002
|
||||
ED 0xFE400354, 0x01AD8002
|
||||
|
||||
LIST "SCIF0 - Serial port for earlyprintk"
|
||||
EB 0xE6053098, 0x11
|
||||
|
|
|
@ -6,13 +6,10 @@ LIST "RWT Setting"
|
|||
EW 0xE6020004, 0xA500
|
||||
EW 0xE6030004, 0xA500
|
||||
|
||||
DD 0x01001000, 0x01001000
|
||||
|
||||
LIST "GPIO Setting"
|
||||
EB 0xE6051013, 0xA2
|
||||
|
||||
LIST "CPG"
|
||||
ED 0xE6150080, 0x00000180
|
||||
ED 0xE61500C0, 0x00000002
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
|
|||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
LIST "SUB/USBClk"
|
||||
ED 0xE6150080, 0x00000180
|
||||
|
||||
LIST "BSC"
|
||||
ED 0xFEC10000, 0x00E0001B
|
||||
|
||||
|
@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
|
|||
ED 0xFE40004C, 0x00110209
|
||||
ED 0xFE400010, 0x00000087
|
||||
|
||||
WAIT 10, 0xFE40009C
|
||||
WAIT 30, 0xFE40009C
|
||||
|
||||
ED 0xFE400084, 0x0000003F
|
||||
EB 0xFE500000, 0x00
|
||||
|
@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
|
|||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xE6150354, 0x00000002
|
||||
ED 0xFE400354, 0x01AD8002
|
||||
|
||||
LIST "SCIF0 - Serial port for earlyprintk"
|
||||
EB 0xE6053098, 0x11
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -17,6 +18,8 @@
|
|||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
#include <mach/tcc-nand.h>
|
||||
#include <mach/tcc8k-regs.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
@ -51,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
|
|||
static void __init tcc8k_map_io(void)
|
||||
{
|
||||
tcc8k_map_common_io();
|
||||
|
||||
/* set PLL0 clock to 96MHz, adapt UART0 divisor */
|
||||
__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
|
||||
__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
|
||||
|
||||
/* set PLL1 clock to 192MHz */
|
||||
__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
|
||||
|
||||
/* set PLL2 clock to 48MHz */
|
||||
__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
|
||||
|
||||
/* with CPU freq higher than 150 MHz, need extra DTCM wait */
|
||||
__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
|
||||
|
||||
/* PLL locking time as specified */
|
||||
udelay(300);
|
||||
}
|
||||
|
||||
MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
|
||||
|
|
|
@ -45,11 +45,12 @@
|
|||
#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
|
||||
#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
|
||||
#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
|
||||
#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
|
||||
#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
|
||||
#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
|
||||
#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
|
||||
|
||||
#define ACLK_MAX_DIV (0xfff + 1)
|
||||
|
||||
/* Crystal frequencies */
|
||||
static unsigned long xi_rate, xti_rate;
|
||||
|
||||
|
@ -106,9 +107,9 @@ static int root_clk_enable(enum root_clks src)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int root_clk_disable(enum root_clks root_src)
|
||||
static int root_clk_disable(enum root_clks src)
|
||||
{
|
||||
switch (root_src) {
|
||||
switch (src) {
|
||||
case CLK_SRC_PLL0: return pll_enable(0, 0);
|
||||
case CLK_SRC_PLL1: return pll_enable(1, 0);
|
||||
case CLK_SRC_PLL2: return pll_enable(2, 0);
|
||||
|
@ -197,7 +198,7 @@ static unsigned long get_rate_pll_div(int pll)
|
|||
addr = CKC_BASE + CLKDIVC1_OFFS;
|
||||
reg = __raw_readl(addr);
|
||||
if (reg & CLKDIVC1_P2E)
|
||||
div = __raw_readl(addr) & 0x3f;
|
||||
div = reg & 0x3f;
|
||||
break;
|
||||
}
|
||||
return get_rate_pll(pll) / (div + 1);
|
||||
|
@ -258,14 +259,19 @@ static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
|
|||
{
|
||||
unsigned long div, src, freq, r1, r2;
|
||||
|
||||
if (!rate)
|
||||
return ACLK_MAX_DIV;
|
||||
|
||||
src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
|
||||
src &= CLK_SRC_MASK;
|
||||
freq = root_clk_get_rate(src);
|
||||
div = freq / rate + 1;
|
||||
div = freq / rate;
|
||||
if (!div)
|
||||
return 1;
|
||||
if (div >= ACLK_MAX_DIV)
|
||||
return ACLK_MAX_DIV;
|
||||
r1 = freq / div;
|
||||
r2 = freq / (div + 1);
|
||||
if (r2 >= rate)
|
||||
return div + 1;
|
||||
if ((rate - r2) < (r1 - rate))
|
||||
return div + 1;
|
||||
|
||||
|
@ -287,7 +293,8 @@ static int aclk_set_rate(struct clk *clk, unsigned long rate)
|
|||
u32 reg;
|
||||
|
||||
reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
|
||||
reg |= aclk_best_div(clk, rate);
|
||||
reg |= aclk_best_div(clk, rate) - 1;
|
||||
__raw_writel(reg, clk->aclkreg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -296,15 +303,22 @@ static unsigned long get_rate_sys(struct clk *clk)
|
|||
unsigned int src;
|
||||
|
||||
src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
|
||||
return root_clk_get_rate(src);
|
||||
return root_clk_get_rate(src);
|
||||
}
|
||||
|
||||
static unsigned long get_rate_bus(struct clk *clk)
|
||||
{
|
||||
unsigned int div;
|
||||
unsigned int reg, sdiv, bdiv, rate;
|
||||
|
||||
div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
|
||||
return get_rate_sys(clk) / (div + 1);
|
||||
reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
|
||||
rate = get_rate_sys(clk);
|
||||
sdiv = (reg >> 20) & 3;
|
||||
if (sdiv)
|
||||
rate /= sdiv + 1;
|
||||
bdiv = (reg >> 4) & 0xff;
|
||||
if (bdiv)
|
||||
rate /= bdiv + 1;
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long get_rate_cpu(struct clk *clk)
|
||||
|
|
|
@ -57,5 +57,6 @@ struct tegra_kbc_platform_data {
|
|||
const struct matrix_keymap_data *keymap_data;
|
||||
|
||||
bool wakeup;
|
||||
bool use_fn_map;
|
||||
};
|
||||
#endif
|
||||
|
|
|
@ -322,15 +322,18 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
|
|||
|
||||
struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
|
||||
{
|
||||
struct omap_mbox *mbox;
|
||||
int ret;
|
||||
struct omap_mbox *_mbox, *mbox = NULL;
|
||||
int i, ret;
|
||||
|
||||
if (!mboxes)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (mbox = *mboxes; mbox; mbox++)
|
||||
if (!strcmp(mbox->name, name))
|
||||
for (i = 0; (_mbox = mboxes[i]); i++) {
|
||||
if (!strcmp(_mbox->name, name)) {
|
||||
mbox = _mbox;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!mbox)
|
||||
return ERR_PTR(-ENOENT);
|
||||
|
|
|
@ -15,6 +15,8 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
/* uart devices */
|
||||
|
||||
static struct platform_device s3c24xx_uart_device0 = {
|
||||
|
|
|
@ -13,6 +13,8 @@
|
|||
.align 2
|
||||
|
||||
ENTRY(_outsl)
|
||||
CC = R2 == 0;
|
||||
IF CC JUMP 1f;
|
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
@ -20,10 +22,12 @@ ENTRY(_outsl)
|
|||
LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
|
||||
.Llong_loop_s: R0 = [P1++];
|
||||
.Llong_loop_e: [P0] = R0;
|
||||
RTS;
|
||||
1: RTS;
|
||||
ENDPROC(_outsl)
|
||||
|
||||
ENTRY(_outsw)
|
||||
CC = R2 == 0;
|
||||
IF CC JUMP 1f;
|
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
@ -31,10 +35,12 @@ ENTRY(_outsw)
|
|||
LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
|
||||
.Lword_loop_s: R0 = W[P1++];
|
||||
.Lword_loop_e: W[P0] = R0;
|
||||
RTS;
|
||||
1: RTS;
|
||||
ENDPROC(_outsw)
|
||||
|
||||
ENTRY(_outsb)
|
||||
CC = R2 == 0;
|
||||
IF CC JUMP 1f;
|
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
@ -42,10 +48,12 @@ ENTRY(_outsb)
|
|||
LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
|
||||
.Lbyte_loop_s: R0 = B[P1++];
|
||||
.Lbyte_loop_e: B[P0] = R0;
|
||||
RTS;
|
||||
1: RTS;
|
||||
ENDPROC(_outsb)
|
||||
|
||||
ENTRY(_outsw_8)
|
||||
CC = R2 == 0;
|
||||
IF CC JUMP 1f;
|
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
@ -56,5 +64,5 @@ ENTRY(_outsw_8)
|
|||
R0 = R0 << 8;
|
||||
R0 = R0 + R1;
|
||||
.Lword8_loop_e: W[P0] = R0;
|
||||
RTS;
|
||||
1: RTS;
|
||||
ENDPROC(_outsw_8)
|
||||
|
|
|
@ -58,6 +58,8 @@
|
|||
1:
|
||||
.ifeqs "\flushins", BROK_FLUSH_INST
|
||||
\flushins [P0++];
|
||||
nop;
|
||||
nop;
|
||||
2: nop;
|
||||
.else
|
||||
2: \flushins [P0++];
|
||||
|
|
|
@ -72,11 +72,6 @@ SECTIONS
|
|||
INIT_TEXT_SECTION(PAGE_SIZE)
|
||||
.init.data : { INIT_DATA }
|
||||
.init.setup : { INIT_SETUP(16) }
|
||||
#ifdef CONFIG_ETRAX_ARCH_V32
|
||||
__start___param = .;
|
||||
__param : { *(__param) }
|
||||
__stop___param = .;
|
||||
#endif
|
||||
.initcall.init : {
|
||||
INIT_CALLS
|
||||
}
|
||||
|
|
|
@ -240,6 +240,12 @@ struct machdep_calls {
|
|||
* claims to support kexec.
|
||||
*/
|
||||
int (*machine_kexec_prepare)(struct kimage *image);
|
||||
|
||||
/* Called to perform the _real_ kexec.
|
||||
* Do NOT allocate memory or fail here. We are past the point of
|
||||
* no return.
|
||||
*/
|
||||
void (*machine_kexec)(struct kimage *image);
|
||||
#endif /* CONFIG_KEXEC */
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
|
|
@ -87,7 +87,10 @@ void machine_kexec(struct kimage *image)
|
|||
|
||||
save_ftrace_enabled = __ftrace_enabled_save();
|
||||
|
||||
default_machine_kexec(image);
|
||||
if (ppc_md.machine_kexec)
|
||||
ppc_md.machine_kexec(image);
|
||||
else
|
||||
default_machine_kexec(image);
|
||||
|
||||
__ftrace_enabled_restore(save_ftrace_enabled);
|
||||
|
||||
|
|
|
@ -353,6 +353,7 @@ static void switch_booke_debug_regs(struct thread_struct *new_thread)
|
|||
prime_debug_regs(new_thread);
|
||||
}
|
||||
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
|
||||
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
||||
static void set_debug_reg_defaults(struct thread_struct *thread)
|
||||
{
|
||||
if (thread->dabr) {
|
||||
|
@ -360,6 +361,7 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
|
|||
set_dabr(0);
|
||||
}
|
||||
}
|
||||
#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
|
||||
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
||||
|
||||
int set_dabr(unsigned long dabr)
|
||||
|
@ -670,11 +672,11 @@ void flush_thread(void)
|
|||
{
|
||||
discard_lazy_cpu_state();
|
||||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINTS
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
flush_ptrace_hw_breakpoint(current);
|
||||
#else /* CONFIG_HAVE_HW_BREAKPOINTS */
|
||||
#else /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
set_debug_reg_defaults(¤t->thread);
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
@ -38,13 +38,11 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
|
|||
* neesd to be flushed. This function will either perform the flush
|
||||
* immediately or will batch it up if the current CPU has an active
|
||||
* batch on it.
|
||||
*
|
||||
* Must be called from within some kind of spinlock/non-preempt region...
|
||||
*/
|
||||
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep, unsigned long pte, int huge)
|
||||
{
|
||||
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
|
||||
struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
|
||||
unsigned long vsid, vaddr;
|
||||
unsigned int psize;
|
||||
int ssize;
|
||||
|
@ -99,6 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
|
|||
*/
|
||||
if (!batch->active) {
|
||||
flush_hash_page(vaddr, rpte, psize, ssize, 0);
|
||||
put_cpu_var(ppc64_tlb_batch);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -127,6 +126,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
|
|||
batch->index = ++i;
|
||||
if (i >= PPC64_TLB_BATCH_NR)
|
||||
__flush_tlb_pending(batch);
|
||||
put_cpu_var(ppc64_tlb_batch);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
extern void __nosave_begin, __nosave_end;
|
||||
extern long __nosave_begin, __nosave_end;
|
||||
extern long __machvec_start, __machvec_end;
|
||||
extern char __uncached_start, __uncached_end;
|
||||
extern char _ebss[];
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <asm/machtypes.h>
|
||||
#include <generated/machtypes.h>
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
|
@ -255,12 +255,17 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
|
|||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
struct platform_device *dev[1];
|
||||
|
||||
if (mach_is_rts7751r2d()) {
|
||||
scif_platform_data.scscr |= SCSCR_CKE1;
|
||||
early_platform_add_devices(&scif_device, 1);
|
||||
dev[0] = &scif_device;
|
||||
early_platform_add_devices(dev, 1);
|
||||
} else {
|
||||
early_platform_add_devices(&sci_device, 1);
|
||||
early_platform_add_devices(&scif_device, 1);
|
||||
dev[0] = &sci_device;
|
||||
early_platform_add_devices(dev, 1);
|
||||
dev[0] = &scif_device;
|
||||
early_platform_add_devices(dev, 1);
|
||||
}
|
||||
|
||||
early_platform_add_devices(sh7750_early_devices,
|
||||
|
|
|
@ -10,6 +10,16 @@
|
|||
void __delay(unsigned long loops)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
/*
|
||||
* ST40-300 appears to have an issue with this code,
|
||||
* normally taking two cycles each loop, as with all
|
||||
* other SH variants. If however the branch and the
|
||||
* delay slot straddle an 8 byte boundary, this increases
|
||||
* to 3 cycles.
|
||||
* This align directive ensures this doesn't occur.
|
||||
*/
|
||||
".balign 8\n\t"
|
||||
|
||||
"tst %0, %0\n\t"
|
||||
"1:\t"
|
||||
"bf/s 1b\n\t"
|
||||
|
|
|
@ -108,7 +108,8 @@ void copy_user_highpage(struct page *to, struct page *from,
|
|||
kunmap_atomic(vfrom, KM_USER0);
|
||||
}
|
||||
|
||||
if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
||||
if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
|
||||
(vma->vm_flags & VM_EXEC))
|
||||
__flush_purge_region(vto, PAGE_SIZE);
|
||||
|
||||
kunmap_atomic(vto, KM_USER1);
|
||||
|
|
|
@ -88,6 +88,7 @@ extern int acpi_disabled;
|
|||
extern int acpi_pci_disabled;
|
||||
extern int acpi_skip_timer_override;
|
||||
extern int acpi_use_timer_override;
|
||||
extern int acpi_fix_pin2_polarity;
|
||||
|
||||
extern u8 acpi_sci_flags;
|
||||
extern int acpi_sci_override_gsi;
|
||||
|
|
|
@ -36,6 +36,11 @@
|
|||
#define MSR_IA32_PERFCTR1 0x000000c2
|
||||
#define MSR_FSB_FREQ 0x000000cd
|
||||
|
||||
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
|
||||
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
|
||||
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
|
||||
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
|
||||
|
||||
#define MSR_MTRRcap 0x000000fe
|
||||
#define MSR_IA32_BBL_CR_CTL 0x00000119
|
||||
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#define ARCH_P4_CNTRVAL_BITS (40)
|
||||
#define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
|
||||
#define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
|
||||
|
||||
#define P4_ESCR_EVENT_MASK 0x7e000000U
|
||||
#define P4_ESCR_EVENT_SHIFT 25
|
||||
|
|
|
@ -34,7 +34,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
|
|||
*/
|
||||
CMOS_WRITE(0, 0xf);
|
||||
|
||||
*((volatile long *)phys_to_virt(apic->trampoline_phys_low)) = 0;
|
||||
*((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0;
|
||||
}
|
||||
|
||||
static inline void __init smpboot_setup_io_apic(void)
|
||||
|
|
|
@ -72,6 +72,7 @@ u8 acpi_sci_flags __initdata;
|
|||
int acpi_sci_override_gsi __initdata;
|
||||
int acpi_skip_timer_override __initdata;
|
||||
int acpi_use_timer_override __initdata;
|
||||
int acpi_fix_pin2_polarity __initdata;
|
||||
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
|
||||
|
@ -415,10 +416,15 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
|
|||
return 0;
|
||||
}
|
||||
|
||||
if (acpi_skip_timer_override &&
|
||||
intsrc->source_irq == 0 && intsrc->global_irq == 2) {
|
||||
printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
|
||||
return 0;
|
||||
if (intsrc->source_irq == 0 && intsrc->global_irq == 2) {
|
||||
if (acpi_skip_timer_override) {
|
||||
printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
|
||||
return 0;
|
||||
}
|
||||
if (acpi_fix_pin2_polarity && (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) {
|
||||
intsrc->inti_flags &= ~ACPI_MADT_POLARITY_MASK;
|
||||
printk(PREFIX "BIOS IRQ0 pin2 override: forcing polarity to high active.\n");
|
||||
}
|
||||
}
|
||||
|
||||
mp_override_legacy_irq(intsrc->source_irq,
|
||||
|
|
|
@ -284,7 +284,7 @@ static int __init apbt_clockevent_register(void)
|
|||
memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
|
||||
|
||||
if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
|
||||
apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
|
||||
adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
|
||||
global_clock_event = &adev->evt;
|
||||
printk(KERN_DEBUG "%s clockevent registered as global\n",
|
||||
global_clock_event->name);
|
||||
|
|
|
@ -158,9 +158,9 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
|
|||
{
|
||||
if (c->x86 == 0x06) {
|
||||
if (cpu_has(c, X86_FEATURE_EST))
|
||||
printk(KERN_WARNING PFX "Warning: EST-capable CPU "
|
||||
"detected. The acpi-cpufreq module offers "
|
||||
"voltage scaling in addition of frequency "
|
||||
printk_once(KERN_WARNING PFX "Warning: EST-capable "
|
||||
"CPU detected. The acpi-cpufreq module offers "
|
||||
"voltage scaling in addition to frequency "
|
||||
"scaling. You should use that instead of "
|
||||
"p4-clockmod, if possible.\n");
|
||||
switch (c->x86_model) {
|
||||
|
|
|
@ -1537,6 +1537,7 @@ static struct notifier_block cpb_nb = {
|
|||
static int __cpuinit powernowk8_init(void)
|
||||
{
|
||||
unsigned int i, supported_cpus = 0, cpu;
|
||||
int rv;
|
||||
|
||||
for_each_online_cpu(i) {
|
||||
int rc;
|
||||
|
@ -1555,14 +1556,14 @@ static int __cpuinit powernowk8_init(void)
|
|||
|
||||
cpb_capable = true;
|
||||
|
||||
register_cpu_notifier(&cpb_nb);
|
||||
|
||||
msrs = msrs_alloc();
|
||||
if (!msrs) {
|
||||
printk(KERN_ERR "%s: Error allocating msrs!\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
register_cpu_notifier(&cpb_nb);
|
||||
|
||||
rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
|
||||
|
||||
for_each_cpu(cpu, cpu_online_mask) {
|
||||
|
@ -1574,7 +1575,13 @@ static int __cpuinit powernowk8_init(void)
|
|||
(cpb_enabled ? "on" : "off"));
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&cpufreq_amd64_driver);
|
||||
rv = cpufreq_register_driver(&cpufreq_amd64_driver);
|
||||
if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) {
|
||||
unregister_cpu_notifier(&cpb_nb);
|
||||
msrs_free(msrs);
|
||||
msrs = NULL;
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
|
||||
/* driver entry point for term */
|
||||
|
|
|
@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* it might be unflagged overflow */
|
||||
rdmsrl(hwc->event_base + hwc->idx, v);
|
||||
if (!(v & ARCH_P4_CNTRVAL_MASK))
|
||||
/*
|
||||
* In some circumstances the overflow might issue an NMI but did
|
||||
* not set P4_CCCR_OVF bit. Because a counter holds a negative value
|
||||
* we simply check for high bit being set, if it's cleared it means
|
||||
* the counter has reached zero value and continued counting before
|
||||
* real NMI signal was received:
|
||||
*/
|
||||
if (!(v & ARCH_P4_UNFLAGGED_BIT))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -143,15 +143,10 @@ static void __init ati_bugs(int num, int slot, int func)
|
|||
|
||||
static u32 __init ati_sbx00_rev(int num, int slot, int func)
|
||||
{
|
||||
u32 old, d;
|
||||
u32 d;
|
||||
|
||||
d = read_pci_config(num, slot, func, 0x70);
|
||||
old = d;
|
||||
d &= ~(1<<8);
|
||||
write_pci_config(num, slot, func, 0x70, d);
|
||||
d = read_pci_config(num, slot, func, 0x8);
|
||||
d &= 0xff;
|
||||
write_pci_config(num, slot, func, 0x70, old);
|
||||
|
||||
return d;
|
||||
}
|
||||
|
@ -160,11 +155,14 @@ static void __init ati_bugs_contd(int num, int slot, int func)
|
|||
{
|
||||
u32 d, rev;
|
||||
|
||||
if (acpi_use_timer_override)
|
||||
rev = ati_sbx00_rev(num, slot, func);
|
||||
if (rev >= 0x40)
|
||||
acpi_fix_pin2_polarity = 1;
|
||||
|
||||
if (rev > 0x13)
|
||||
return;
|
||||
|
||||
rev = ati_sbx00_rev(num, slot, func);
|
||||
if (rev > 0x13)
|
||||
if (acpi_use_timer_override)
|
||||
return;
|
||||
|
||||
/* check for IRQ0 interrupt swap */
|
||||
|
|
|
@ -285,6 +285,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
|
|||
DMI_MATCH(DMI_BOARD_NAME, "P4S800"),
|
||||
},
|
||||
},
|
||||
{ /* Handle problems with rebooting on VersaLogic Menlow boards */
|
||||
.callback = set_bios_reboot,
|
||||
.ident = "VersaLogic Menlow based board",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_VENDOR, "VersaLogic Corporation"),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "VersaLogic Menlow board"),
|
||||
},
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
@ -2777,6 +2777,8 @@ static int dr_interception(struct vcpu_svm *svm)
|
|||
kvm_register_write(&svm->vcpu, reg, val);
|
||||
}
|
||||
|
||||
skip_emulated_instruction(&svm->vcpu);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
|
@ -140,8 +140,7 @@ void * __init prom_early_alloc(unsigned long size)
|
|||
* wasted bootmem) and hand off chunks of it to callers.
|
||||
*/
|
||||
res = alloc_bootmem(chunk_size);
|
||||
if (!res)
|
||||
return NULL;
|
||||
BUG_ON(!res);
|
||||
prom_early_allocated += chunk_size;
|
||||
memset(res, 0, chunk_size);
|
||||
free_mem = chunk_size;
|
||||
|
|
|
@ -352,7 +352,7 @@ void blk_start_queue(struct request_queue *q)
|
|||
WARN_ON(!irqs_disabled());
|
||||
|
||||
queue_flag_clear(QUEUE_FLAG_STOPPED, q);
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, false);
|
||||
}
|
||||
EXPORT_SYMBOL(blk_start_queue);
|
||||
|
||||
|
@ -403,13 +403,14 @@ EXPORT_SYMBOL(blk_sync_queue);
|
|||
/**
|
||||
* __blk_run_queue - run a single device queue
|
||||
* @q: The queue to run
|
||||
* @force_kblockd: Don't run @q->request_fn directly. Use kblockd.
|
||||
*
|
||||
* Description:
|
||||
* See @blk_run_queue. This variant must be called with the queue lock
|
||||
* held and interrupts disabled.
|
||||
*
|
||||
*/
|
||||
void __blk_run_queue(struct request_queue *q)
|
||||
void __blk_run_queue(struct request_queue *q, bool force_kblockd)
|
||||
{
|
||||
blk_remove_plug(q);
|
||||
|
||||
|
@ -423,7 +424,7 @@ void __blk_run_queue(struct request_queue *q)
|
|||
* Only recurse once to avoid overrunning the stack, let the unplug
|
||||
* handling reinvoke the handler shortly if we already got there.
|
||||
*/
|
||||
if (!queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
|
||||
if (!force_kblockd && !queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
|
||||
q->request_fn(q);
|
||||
queue_flag_clear(QUEUE_FLAG_REENTER, q);
|
||||
} else {
|
||||
|
@ -446,7 +447,7 @@ void blk_run_queue(struct request_queue *q)
|
|||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(q->queue_lock, flags);
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, false);
|
||||
spin_unlock_irqrestore(q->queue_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(blk_run_queue);
|
||||
|
@ -1053,7 +1054,7 @@ void blk_insert_request(struct request_queue *q, struct request *rq,
|
|||
|
||||
drive_stat_acct(rq, 1);
|
||||
__elv_add_request(q, rq, where, 0);
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, false);
|
||||
spin_unlock_irqrestore(q->queue_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(blk_insert_request);
|
||||
|
@ -2610,13 +2611,6 @@ int kblockd_schedule_work(struct request_queue *q, struct work_struct *work)
|
|||
}
|
||||
EXPORT_SYMBOL(kblockd_schedule_work);
|
||||
|
||||
int kblockd_schedule_delayed_work(struct request_queue *q,
|
||||
struct delayed_work *dwork, unsigned long delay)
|
||||
{
|
||||
return queue_delayed_work(kblockd_workqueue, dwork, delay);
|
||||
}
|
||||
EXPORT_SYMBOL(kblockd_schedule_delayed_work);
|
||||
|
||||
int __init blk_dev_init(void)
|
||||
{
|
||||
BUILD_BUG_ON(__REQ_NR_BITS > 8 *
|
||||
|
|
|
@ -66,10 +66,12 @@ static void blk_flush_complete_seq_end_io(struct request_queue *q,
|
|||
|
||||
/*
|
||||
* Moving a request silently to empty queue_head may stall the
|
||||
* queue. Kick the queue in those cases.
|
||||
* queue. Kick the queue in those cases. This function is called
|
||||
* from request completion path and calling directly into
|
||||
* request_fn may confuse the driver. Always use kblockd.
|
||||
*/
|
||||
if (was_empty && next_rq)
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, true);
|
||||
}
|
||||
|
||||
static void pre_flush_end_io(struct request *rq, int error)
|
||||
|
@ -130,7 +132,7 @@ static struct request *queue_next_fseq(struct request_queue *q)
|
|||
BUG();
|
||||
}
|
||||
|
||||
elv_insert(q, rq, ELEVATOR_INSERT_FRONT);
|
||||
elv_insert(q, rq, ELEVATOR_INSERT_REQUEUE);
|
||||
return rq;
|
||||
}
|
||||
|
||||
|
|
|
@ -132,7 +132,7 @@ static void bio_batch_end_io(struct bio *bio, int err)
|
|||
}
|
||||
|
||||
/**
|
||||
* blkdev_issue_zeroout generate number of zero filed write bios
|
||||
* blkdev_issue_zeroout - generate number of zero filed write bios
|
||||
* @bdev: blockdev to issue
|
||||
* @sector: start sector
|
||||
* @nr_sects: number of sectors to write
|
||||
|
|
|
@ -20,6 +20,11 @@ static int throtl_quantum = 32;
|
|||
/* Throttling is performed over 100ms slice and after that slice is renewed */
|
||||
static unsigned long throtl_slice = HZ/10; /* 100 ms */
|
||||
|
||||
/* A workqueue to queue throttle related work */
|
||||
static struct workqueue_struct *kthrotld_workqueue;
|
||||
static void throtl_schedule_delayed_work(struct throtl_data *td,
|
||||
unsigned long delay);
|
||||
|
||||
struct throtl_rb_root {
|
||||
struct rb_root rb;
|
||||
struct rb_node *left;
|
||||
|
@ -345,10 +350,9 @@ static void throtl_schedule_next_dispatch(struct throtl_data *td)
|
|||
update_min_dispatch_time(st);
|
||||
|
||||
if (time_before_eq(st->min_disptime, jiffies))
|
||||
throtl_schedule_delayed_work(td->queue, 0);
|
||||
throtl_schedule_delayed_work(td, 0);
|
||||
else
|
||||
throtl_schedule_delayed_work(td->queue,
|
||||
(st->min_disptime - jiffies));
|
||||
throtl_schedule_delayed_work(td, (st->min_disptime - jiffies));
|
||||
}
|
||||
|
||||
static inline void
|
||||
|
@ -815,10 +819,10 @@ void blk_throtl_work(struct work_struct *work)
|
|||
}
|
||||
|
||||
/* Call with queue lock held */
|
||||
void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
|
||||
static void
|
||||
throtl_schedule_delayed_work(struct throtl_data *td, unsigned long delay)
|
||||
{
|
||||
|
||||
struct throtl_data *td = q->td;
|
||||
struct delayed_work *dwork = &td->throtl_work;
|
||||
|
||||
if (total_nr_queued(td) > 0) {
|
||||
|
@ -827,12 +831,11 @@ void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
|
|||
* Cancel that and schedule a new one.
|
||||
*/
|
||||
__cancel_delayed_work(dwork);
|
||||
kblockd_schedule_delayed_work(q, dwork, delay);
|
||||
queue_delayed_work(kthrotld_workqueue, dwork, delay);
|
||||
throtl_log(td, "schedule work. delay=%lu jiffies=%lu",
|
||||
delay, jiffies);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(throtl_schedule_delayed_work);
|
||||
|
||||
static void
|
||||
throtl_destroy_tg(struct throtl_data *td, struct throtl_grp *tg)
|
||||
|
@ -920,7 +923,7 @@ static void throtl_update_blkio_group_read_bps(void *key,
|
|||
smp_mb__after_atomic_inc();
|
||||
|
||||
/* Schedule a work now to process the limit change */
|
||||
throtl_schedule_delayed_work(td->queue, 0);
|
||||
throtl_schedule_delayed_work(td, 0);
|
||||
}
|
||||
|
||||
static void throtl_update_blkio_group_write_bps(void *key,
|
||||
|
@ -934,7 +937,7 @@ static void throtl_update_blkio_group_write_bps(void *key,
|
|||
smp_mb__before_atomic_inc();
|
||||
atomic_inc(&td->limits_changed);
|
||||
smp_mb__after_atomic_inc();
|
||||
throtl_schedule_delayed_work(td->queue, 0);
|
||||
throtl_schedule_delayed_work(td, 0);
|
||||
}
|
||||
|
||||
static void throtl_update_blkio_group_read_iops(void *key,
|
||||
|
@ -948,7 +951,7 @@ static void throtl_update_blkio_group_read_iops(void *key,
|
|||
smp_mb__before_atomic_inc();
|
||||
atomic_inc(&td->limits_changed);
|
||||
smp_mb__after_atomic_inc();
|
||||
throtl_schedule_delayed_work(td->queue, 0);
|
||||
throtl_schedule_delayed_work(td, 0);
|
||||
}
|
||||
|
||||
static void throtl_update_blkio_group_write_iops(void *key,
|
||||
|
@ -962,7 +965,7 @@ static void throtl_update_blkio_group_write_iops(void *key,
|
|||
smp_mb__before_atomic_inc();
|
||||
atomic_inc(&td->limits_changed);
|
||||
smp_mb__after_atomic_inc();
|
||||
throtl_schedule_delayed_work(td->queue, 0);
|
||||
throtl_schedule_delayed_work(td, 0);
|
||||
}
|
||||
|
||||
void throtl_shutdown_timer_wq(struct request_queue *q)
|
||||
|
@ -1135,6 +1138,10 @@ void blk_throtl_exit(struct request_queue *q)
|
|||
|
||||
static int __init throtl_init(void)
|
||||
{
|
||||
kthrotld_workqueue = alloc_workqueue("kthrotld", WQ_MEM_RECLAIM, 0);
|
||||
if (!kthrotld_workqueue)
|
||||
panic("Failed to create kthrotld\n");
|
||||
|
||||
blkio_policy_register(&blkio_policy_throtl);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -3355,7 +3355,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
|
|||
cfqd->busy_queues > 1) {
|
||||
cfq_del_timer(cfqd, cfqq);
|
||||
cfq_clear_cfqq_wait_request(cfqq);
|
||||
__blk_run_queue(cfqd->queue);
|
||||
__blk_run_queue(cfqd->queue, false);
|
||||
} else {
|
||||
cfq_blkiocg_update_idle_time_stats(
|
||||
&cfqq->cfqg->blkg);
|
||||
|
@ -3370,7 +3370,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
|
|||
* this new queue is RT and the current one is BE
|
||||
*/
|
||||
cfq_preempt_queue(cfqd, cfqq);
|
||||
__blk_run_queue(cfqd->queue);
|
||||
__blk_run_queue(cfqd->queue, false);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -3731,7 +3731,7 @@ static void cfq_kick_queue(struct work_struct *work)
|
|||
struct request_queue *q = cfqd->queue;
|
||||
|
||||
spin_lock_irq(q->queue_lock);
|
||||
__blk_run_queue(cfqd->queue);
|
||||
__blk_run_queue(cfqd->queue, false);
|
||||
spin_unlock_irq(q->queue_lock);
|
||||
}
|
||||
|
||||
|
|
|
@ -602,7 +602,7 @@ void elv_quiesce_start(struct request_queue *q)
|
|||
*/
|
||||
elv_drain_elevator(q);
|
||||
while (q->rq.elvpriv) {
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, false);
|
||||
spin_unlock_irq(q->queue_lock);
|
||||
msleep(10);
|
||||
spin_lock_irq(q->queue_lock);
|
||||
|
@ -651,7 +651,7 @@ void elv_insert(struct request_queue *q, struct request *rq, int where)
|
|||
* with anything. There's no point in delaying queue
|
||||
* processing.
|
||||
*/
|
||||
__blk_run_queue(q);
|
||||
__blk_run_queue(q, false);
|
||||
break;
|
||||
|
||||
case ELEVATOR_INSERT_SORT:
|
||||
|
|
|
@ -1355,7 +1355,7 @@ int invalidate_partition(struct gendisk *disk, int partno)
|
|||
struct block_device *bdev = bdget_disk(disk, partno);
|
||||
if (bdev) {
|
||||
fsync_bdev(bdev);
|
||||
res = __invalidate_device(bdev);
|
||||
res = __invalidate_device(bdev, true);
|
||||
bdput(bdev);
|
||||
}
|
||||
return res;
|
||||
|
|
|
@ -294,9 +294,11 @@ int blkdev_ioctl(struct block_device *bdev, fmode_t mode, unsigned cmd,
|
|||
return -EINVAL;
|
||||
if (get_user(n, (int __user *) arg))
|
||||
return -EFAULT;
|
||||
if (!(mode & FMODE_EXCL) &&
|
||||
blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
|
||||
return -EBUSY;
|
||||
if (!(mode & FMODE_EXCL)) {
|
||||
bdgrab(bdev);
|
||||
if (blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
|
||||
return -EBUSY;
|
||||
}
|
||||
ret = set_blocksize(bdev, n);
|
||||
if (!(mode & FMODE_EXCL))
|
||||
blkdev_put(bdev, mode | FMODE_EXCL);
|
||||
|
|
|
@ -416,10 +416,15 @@ struct acpi_gpe_handler_info {
|
|||
u8 originally_enabled; /* True if GPE was originally enabled */
|
||||
};
|
||||
|
||||
struct acpi_gpe_notify_object {
|
||||
struct acpi_namespace_node *node;
|
||||
struct acpi_gpe_notify_object *next;
|
||||
};
|
||||
|
||||
union acpi_gpe_dispatch_info {
|
||||
struct acpi_namespace_node *method_node; /* Method node for this GPE level */
|
||||
struct acpi_gpe_handler_info *handler; /* Installed GPE handler */
|
||||
struct acpi_namespace_node *device_node; /* Parent _PRW device for implicit notify */
|
||||
struct acpi_gpe_notify_object device; /* List of _PRW devices for implicit notify */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -457,6 +457,7 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
|
|||
acpi_status status;
|
||||
struct acpi_gpe_event_info *local_gpe_event_info;
|
||||
struct acpi_evaluate_info *info;
|
||||
struct acpi_gpe_notify_object *notify_object;
|
||||
|
||||
ACPI_FUNCTION_TRACE(ev_asynch_execute_gpe_method);
|
||||
|
||||
|
@ -508,10 +509,18 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
|
|||
* from this thread -- because handlers may in turn run other
|
||||
* control methods.
|
||||
*/
|
||||
status =
|
||||
acpi_ev_queue_notify_request(local_gpe_event_info->dispatch.
|
||||
device_node,
|
||||
ACPI_NOTIFY_DEVICE_WAKE);
|
||||
status = acpi_ev_queue_notify_request(
|
||||
local_gpe_event_info->dispatch.device.node,
|
||||
ACPI_NOTIFY_DEVICE_WAKE);
|
||||
|
||||
notify_object = local_gpe_event_info->dispatch.device.next;
|
||||
while (ACPI_SUCCESS(status) && notify_object) {
|
||||
status = acpi_ev_queue_notify_request(
|
||||
notify_object->node,
|
||||
ACPI_NOTIFY_DEVICE_WAKE);
|
||||
notify_object = notify_object->next;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case ACPI_GPE_DISPATCH_METHOD:
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue