PCI: Fix typos in docs and comments
Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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Bjorn Helgaas
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2b4af4b398
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86b4ad7d67
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@ -17,7 +17,7 @@ chipsets are able to deal with these errors; these include PCI-E chipsets,
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and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
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pSeries boxes. A typical action taken is to disconnect the affected device,
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halting all I/O to it. The goal of a disconnection is to avoid system
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corruption; for example, to halt system memory corruption due to DMA's
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corruption; for example, to halt system memory corruption due to DMAs
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to "wild" addresses. Typically, a reconnection mechanism is also
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offered, so that the affected PCI device(s) are reset and put back
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into working condition. The reset phase requires coordination
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@ -178,9 +178,9 @@ is STEP 6 (Permanent Failure).
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complex and not worth implementing.
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The current powerpc implementation doesn't much care if the device
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attempts I/O at this point, or not. I/O's will fail, returning
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attempts I/O at this point, or not. I/Os will fail, returning
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a value of 0xff on read, and writes will be dropped. If more than
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EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
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EEH_MAX_FAILS I/Os are attempted to a frozen adapter, EEH
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assumes that the device driver has gone into an infinite loop
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and prints an error to syslog. A reboot is then required to
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get the device working again.
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@ -204,7 +204,7 @@ instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
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.. note::
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The following is proposed; no platform implements this yet:
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Proposal: All I/O's should be done _synchronously_ from within
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Proposal: All I/Os should be done _synchronously_ from within
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this callback, errors triggered by them will be returned via
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the normal pci_check_whatever() API, no new error_detected()
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callback will be issued due to an error happening here. However,
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@ -258,7 +258,7 @@ Powerpc platforms implement two levels of slot reset:
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soft reset(default) and fundamental(optional) reset.
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Powerpc soft reset consists of asserting the adapter #RST line and then
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restoring the PCI BAR's and PCI configuration header to a state
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restoring the PCI BARs and PCI configuration header to a state
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that is equivalent to what it would be after a fresh system
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power-on followed by power-on BIOS/system firmware initialization.
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Soft reset is also known as hot-reset.
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@ -362,7 +362,7 @@ permanent failure in some way. If the device is hotplug-capable,
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the operator will probably want to remove and replace the device.
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Note, however, not all failures are truly "permanent". Some are
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caused by over-heating, some by a poorly seated card. Many
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PCI error events are caused by software bugs, e.g. DMA's to
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PCI error events are caused by software bugs, e.g. DMAs to
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wild addresses or bogus split transactions due to programming
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errors. See the discussion in Documentation/powerpc/eeh-pci-error-recovery.rst
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for additional detail on real-life experience of the causes of
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@ -32,7 +32,7 @@
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#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
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(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
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/* Root Port Requestor ID Register */
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/* Root Port Requester ID Register */
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#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
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#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
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#define CDNS_PCIE_LM_RP_RID_SHIFT 0
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@ -986,22 +986,22 @@ static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf,
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/*==== virtual PCI bus driver, which only load virtual NTB PCI driver ====*/
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static u32 pci_space[] = {
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0xffffffff, /*DeviceID, Vendor ID*/
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0, /*Status, Command*/
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0xffffffff, /*Class code, subclass, prog if, revision id*/
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0x40, /*bist, header type, latency Timer, cache line size*/
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0, /*BAR 0*/
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0, /*BAR 1*/
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0, /*BAR 2*/
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0, /*BAR 3*/
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0, /*BAR 4*/
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0, /*BAR 5*/
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0, /*Cardbus cis point*/
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0, /*Subsystem ID Subystem vendor id*/
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0, /*ROM Base Address*/
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0, /*Reserved, Cap. Point*/
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0, /*Reserved,*/
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0, /*Max Lat, Min Gnt, interrupt pin, interrupt line*/
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0xffffffff, /* Device ID, Vendor ID */
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0, /* Status, Command */
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0xffffffff, /* Base Class, Subclass, Prog Intf, Revision ID */
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0x40, /* BIST, Header Type, Latency Timer, Cache Line Size */
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0, /* BAR 0 */
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0, /* BAR 1 */
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0, /* BAR 2 */
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0, /* BAR 3 */
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0, /* BAR 4 */
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0, /* BAR 5 */
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0, /* Cardbus CIS Pointer */
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0, /* Subsystem ID, Subsystem Vendor ID */
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0, /* ROM Base Address */
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0, /* Reserved, Capabilities Pointer */
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0, /* Reserved */
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0, /* Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line */
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};
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
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@ -336,7 +336,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
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if (!irq_domain_is_msi_parent(domain)) {
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/*
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* For "global" PCI/MSI interrupt domains the associated
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* msi_domain_info::flags is the authoritive source of
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* msi_domain_info::flags is the authoritative source of
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* information.
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*/
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info = domain->host_data;
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@ -344,7 +344,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
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} else {
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/*
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* For MSI parent domains the supported feature set
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* is avaliable in the parent ops. This makes checks
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* is available in the parent ops. This makes checks
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* possible before actually instantiating the
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* per device domain because the parent is never
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* expanding the PCI/MSI functionality.
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@ -435,7 +435,7 @@ static const struct pci_p2pdma_whitelist_entry {
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/* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */
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{PCI_VENDOR_ID_INTEL, 0x2f00, REQ_SAME_HOST_BRIDGE},
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{PCI_VENDOR_ID_INTEL, 0x2f01, REQ_SAME_HOST_BRIDGE},
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/* Intel SkyLake-E */
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/* Intel Skylake-E */
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{PCI_VENDOR_ID_INTEL, 0x2030, 0},
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{PCI_VENDOR_ID_INTEL, 0x2031, 0},
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{PCI_VENDOR_ID_INTEL, 0x2032, 0},
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@ -1290,7 +1290,7 @@ end:
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*
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* Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
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* to confirm the state change, restore its BARs if they might be lost and
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* reconfigure ASPM in acordance with the new power state.
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* reconfigure ASPM in accordance with the new power state.
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*
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* If pci_restore_state() is going to be called right after a power state change
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* to D0, it is more efficient to use pci_power_up() directly instead of this
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@ -2136,7 +2136,7 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
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{
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struct pci_dev *root;
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/* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
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/* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */
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if (dev->is_virtfn)
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return;
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@ -362,7 +362,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_d
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#endif
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/*
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* Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
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* Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear
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* for some HT machines to use C4 w/o hanging.
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*/
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static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
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@ -375,7 +375,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
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pm1a = inw(pmbase);
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if (pm1a & 0x10) {
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pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
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pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n");
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outw(0x10, pmbase);
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}
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}
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@ -3073,7 +3073,7 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
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/*
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* HT MSI mapping should be disabled on devices that are below
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* a non-Hypertransport host bridge. Locate the host bridge...
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* a non-HyperTransport host bridge. Locate the host bridge.
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*/
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host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
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PCI_DEVFN(0, 0));
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@ -5729,7 +5729,7 @@ int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
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/*
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* Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
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* NT endpoints via the internal switch fabric. These IDs replace the
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* originating requestor ID TLPs which access host memory on peer NTB
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* originating Requester ID TLPs which access host memory on peer NTB
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* ports. Therefore, all proxy IDs must be aliased to the NTB device
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* to permit access when the IOMMU is turned on.
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*/
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@ -1799,7 +1799,7 @@ static void remove_dev_resources(struct pci_dev *dev, struct resource *io,
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* Make sure prefetchable memory is reduced from
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* the correct resource. Specifically we put 32-bit
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* prefetchable memory in non-prefetchable window
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* if there is an 64-bit pretchable window.
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* if there is an 64-bit prefetchable window.
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*
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* See comments in __pci_bus_size_bridges() for
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* more information.
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