PCI: Fix typos in docs and comments
Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
parent
2b4af4b398
commit
86b4ad7d67
|
@ -17,7 +17,7 @@ chipsets are able to deal with these errors; these include PCI-E chipsets,
|
||||||
and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
|
and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
|
||||||
pSeries boxes. A typical action taken is to disconnect the affected device,
|
pSeries boxes. A typical action taken is to disconnect the affected device,
|
||||||
halting all I/O to it. The goal of a disconnection is to avoid system
|
halting all I/O to it. The goal of a disconnection is to avoid system
|
||||||
corruption; for example, to halt system memory corruption due to DMA's
|
corruption; for example, to halt system memory corruption due to DMAs
|
||||||
to "wild" addresses. Typically, a reconnection mechanism is also
|
to "wild" addresses. Typically, a reconnection mechanism is also
|
||||||
offered, so that the affected PCI device(s) are reset and put back
|
offered, so that the affected PCI device(s) are reset and put back
|
||||||
into working condition. The reset phase requires coordination
|
into working condition. The reset phase requires coordination
|
||||||
|
@ -178,9 +178,9 @@ is STEP 6 (Permanent Failure).
|
||||||
complex and not worth implementing.
|
complex and not worth implementing.
|
||||||
|
|
||||||
The current powerpc implementation doesn't much care if the device
|
The current powerpc implementation doesn't much care if the device
|
||||||
attempts I/O at this point, or not. I/O's will fail, returning
|
attempts I/O at this point, or not. I/Os will fail, returning
|
||||||
a value of 0xff on read, and writes will be dropped. If more than
|
a value of 0xff on read, and writes will be dropped. If more than
|
||||||
EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
|
EEH_MAX_FAILS I/Os are attempted to a frozen adapter, EEH
|
||||||
assumes that the device driver has gone into an infinite loop
|
assumes that the device driver has gone into an infinite loop
|
||||||
and prints an error to syslog. A reboot is then required to
|
and prints an error to syslog. A reboot is then required to
|
||||||
get the device working again.
|
get the device working again.
|
||||||
|
@ -204,7 +204,7 @@ instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
|
||||||
.. note::
|
.. note::
|
||||||
|
|
||||||
The following is proposed; no platform implements this yet:
|
The following is proposed; no platform implements this yet:
|
||||||
Proposal: All I/O's should be done _synchronously_ from within
|
Proposal: All I/Os should be done _synchronously_ from within
|
||||||
this callback, errors triggered by them will be returned via
|
this callback, errors triggered by them will be returned via
|
||||||
the normal pci_check_whatever() API, no new error_detected()
|
the normal pci_check_whatever() API, no new error_detected()
|
||||||
callback will be issued due to an error happening here. However,
|
callback will be issued due to an error happening here. However,
|
||||||
|
@ -258,7 +258,7 @@ Powerpc platforms implement two levels of slot reset:
|
||||||
soft reset(default) and fundamental(optional) reset.
|
soft reset(default) and fundamental(optional) reset.
|
||||||
|
|
||||||
Powerpc soft reset consists of asserting the adapter #RST line and then
|
Powerpc soft reset consists of asserting the adapter #RST line and then
|
||||||
restoring the PCI BAR's and PCI configuration header to a state
|
restoring the PCI BARs and PCI configuration header to a state
|
||||||
that is equivalent to what it would be after a fresh system
|
that is equivalent to what it would be after a fresh system
|
||||||
power-on followed by power-on BIOS/system firmware initialization.
|
power-on followed by power-on BIOS/system firmware initialization.
|
||||||
Soft reset is also known as hot-reset.
|
Soft reset is also known as hot-reset.
|
||||||
|
@ -362,7 +362,7 @@ permanent failure in some way. If the device is hotplug-capable,
|
||||||
the operator will probably want to remove and replace the device.
|
the operator will probably want to remove and replace the device.
|
||||||
Note, however, not all failures are truly "permanent". Some are
|
Note, however, not all failures are truly "permanent". Some are
|
||||||
caused by over-heating, some by a poorly seated card. Many
|
caused by over-heating, some by a poorly seated card. Many
|
||||||
PCI error events are caused by software bugs, e.g. DMA's to
|
PCI error events are caused by software bugs, e.g. DMAs to
|
||||||
wild addresses or bogus split transactions due to programming
|
wild addresses or bogus split transactions due to programming
|
||||||
errors. See the discussion in Documentation/powerpc/eeh-pci-error-recovery.rst
|
errors. See the discussion in Documentation/powerpc/eeh-pci-error-recovery.rst
|
||||||
for additional detail on real-life experience of the causes of
|
for additional detail on real-life experience of the causes of
|
||||||
|
|
|
@ -32,7 +32,7 @@
|
||||||
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
|
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
|
||||||
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
|
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
|
||||||
|
|
||||||
/* Root Port Requestor ID Register */
|
/* Root Port Requester ID Register */
|
||||||
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
|
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
|
||||||
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
|
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
|
||||||
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
|
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
|
||||||
|
|
|
@ -986,22 +986,22 @@ static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf,
|
||||||
/*==== virtual PCI bus driver, which only load virtual NTB PCI driver ====*/
|
/*==== virtual PCI bus driver, which only load virtual NTB PCI driver ====*/
|
||||||
|
|
||||||
static u32 pci_space[] = {
|
static u32 pci_space[] = {
|
||||||
0xffffffff, /*DeviceID, Vendor ID*/
|
0xffffffff, /* Device ID, Vendor ID */
|
||||||
0, /*Status, Command*/
|
0, /* Status, Command */
|
||||||
0xffffffff, /*Class code, subclass, prog if, revision id*/
|
0xffffffff, /* Base Class, Subclass, Prog Intf, Revision ID */
|
||||||
0x40, /*bist, header type, latency Timer, cache line size*/
|
0x40, /* BIST, Header Type, Latency Timer, Cache Line Size */
|
||||||
0, /*BAR 0*/
|
0, /* BAR 0 */
|
||||||
0, /*BAR 1*/
|
0, /* BAR 1 */
|
||||||
0, /*BAR 2*/
|
0, /* BAR 2 */
|
||||||
0, /*BAR 3*/
|
0, /* BAR 3 */
|
||||||
0, /*BAR 4*/
|
0, /* BAR 4 */
|
||||||
0, /*BAR 5*/
|
0, /* BAR 5 */
|
||||||
0, /*Cardbus cis point*/
|
0, /* Cardbus CIS Pointer */
|
||||||
0, /*Subsystem ID Subystem vendor id*/
|
0, /* Subsystem ID, Subsystem Vendor ID */
|
||||||
0, /*ROM Base Address*/
|
0, /* ROM Base Address */
|
||||||
0, /*Reserved, Cap. Point*/
|
0, /* Reserved, Capabilities Pointer */
|
||||||
0, /*Reserved,*/
|
0, /* Reserved */
|
||||||
0, /*Max Lat, Min Gnt, interrupt pin, interrupt line*/
|
0, /* Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
|
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
|
||||||
|
|
|
@ -336,7 +336,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
|
||||||
if (!irq_domain_is_msi_parent(domain)) {
|
if (!irq_domain_is_msi_parent(domain)) {
|
||||||
/*
|
/*
|
||||||
* For "global" PCI/MSI interrupt domains the associated
|
* For "global" PCI/MSI interrupt domains the associated
|
||||||
* msi_domain_info::flags is the authoritive source of
|
* msi_domain_info::flags is the authoritative source of
|
||||||
* information.
|
* information.
|
||||||
*/
|
*/
|
||||||
info = domain->host_data;
|
info = domain->host_data;
|
||||||
|
@ -344,7 +344,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
|
||||||
} else {
|
} else {
|
||||||
/*
|
/*
|
||||||
* For MSI parent domains the supported feature set
|
* For MSI parent domains the supported feature set
|
||||||
* is avaliable in the parent ops. This makes checks
|
* is available in the parent ops. This makes checks
|
||||||
* possible before actually instantiating the
|
* possible before actually instantiating the
|
||||||
* per device domain because the parent is never
|
* per device domain because the parent is never
|
||||||
* expanding the PCI/MSI functionality.
|
* expanding the PCI/MSI functionality.
|
||||||
|
|
|
@ -435,7 +435,7 @@ static const struct pci_p2pdma_whitelist_entry {
|
||||||
/* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */
|
/* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */
|
||||||
{PCI_VENDOR_ID_INTEL, 0x2f00, REQ_SAME_HOST_BRIDGE},
|
{PCI_VENDOR_ID_INTEL, 0x2f00, REQ_SAME_HOST_BRIDGE},
|
||||||
{PCI_VENDOR_ID_INTEL, 0x2f01, REQ_SAME_HOST_BRIDGE},
|
{PCI_VENDOR_ID_INTEL, 0x2f01, REQ_SAME_HOST_BRIDGE},
|
||||||
/* Intel SkyLake-E */
|
/* Intel Skylake-E */
|
||||||
{PCI_VENDOR_ID_INTEL, 0x2030, 0},
|
{PCI_VENDOR_ID_INTEL, 0x2030, 0},
|
||||||
{PCI_VENDOR_ID_INTEL, 0x2031, 0},
|
{PCI_VENDOR_ID_INTEL, 0x2031, 0},
|
||||||
{PCI_VENDOR_ID_INTEL, 0x2032, 0},
|
{PCI_VENDOR_ID_INTEL, 0x2032, 0},
|
||||||
|
|
|
@ -1290,7 +1290,7 @@ end:
|
||||||
*
|
*
|
||||||
* Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
|
* Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
|
||||||
* to confirm the state change, restore its BARs if they might be lost and
|
* to confirm the state change, restore its BARs if they might be lost and
|
||||||
* reconfigure ASPM in acordance with the new power state.
|
* reconfigure ASPM in accordance with the new power state.
|
||||||
*
|
*
|
||||||
* If pci_restore_state() is going to be called right after a power state change
|
* If pci_restore_state() is going to be called right after a power state change
|
||||||
* to D0, it is more efficient to use pci_power_up() directly instead of this
|
* to D0, it is more efficient to use pci_power_up() directly instead of this
|
||||||
|
|
|
@ -2136,7 +2136,7 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
|
||||||
{
|
{
|
||||||
struct pci_dev *root;
|
struct pci_dev *root;
|
||||||
|
|
||||||
/* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
|
/* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */
|
||||||
if (dev->is_virtfn)
|
if (dev->is_virtfn)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
|
@ -362,7 +362,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_d
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
|
* Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear
|
||||||
* for some HT machines to use C4 w/o hanging.
|
* for some HT machines to use C4 w/o hanging.
|
||||||
*/
|
*/
|
||||||
static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
|
static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
|
||||||
|
@ -375,7 +375,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
|
||||||
pm1a = inw(pmbase);
|
pm1a = inw(pmbase);
|
||||||
|
|
||||||
if (pm1a & 0x10) {
|
if (pm1a & 0x10) {
|
||||||
pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
|
pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n");
|
||||||
outw(0x10, pmbase);
|
outw(0x10, pmbase);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -3073,7 +3073,7 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* HT MSI mapping should be disabled on devices that are below
|
* HT MSI mapping should be disabled on devices that are below
|
||||||
* a non-Hypertransport host bridge. Locate the host bridge...
|
* a non-HyperTransport host bridge. Locate the host bridge.
|
||||||
*/
|
*/
|
||||||
host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
|
host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
|
||||||
PCI_DEVFN(0, 0));
|
PCI_DEVFN(0, 0));
|
||||||
|
@ -5729,7 +5729,7 @@ int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
|
||||||
/*
|
/*
|
||||||
* Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
|
* Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
|
||||||
* NT endpoints via the internal switch fabric. These IDs replace the
|
* NT endpoints via the internal switch fabric. These IDs replace the
|
||||||
* originating requestor ID TLPs which access host memory on peer NTB
|
* originating Requester ID TLPs which access host memory on peer NTB
|
||||||
* ports. Therefore, all proxy IDs must be aliased to the NTB device
|
* ports. Therefore, all proxy IDs must be aliased to the NTB device
|
||||||
* to permit access when the IOMMU is turned on.
|
* to permit access when the IOMMU is turned on.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -1799,7 +1799,7 @@ static void remove_dev_resources(struct pci_dev *dev, struct resource *io,
|
||||||
* Make sure prefetchable memory is reduced from
|
* Make sure prefetchable memory is reduced from
|
||||||
* the correct resource. Specifically we put 32-bit
|
* the correct resource. Specifically we put 32-bit
|
||||||
* prefetchable memory in non-prefetchable window
|
* prefetchable memory in non-prefetchable window
|
||||||
* if there is an 64-bit pretchable window.
|
* if there is an 64-bit prefetchable window.
|
||||||
*
|
*
|
||||||
* See comments in __pci_bus_size_bridges() for
|
* See comments in __pci_bus_size_bridges() for
|
||||||
* more information.
|
* more information.
|
||||||
|
|
Loading…
Reference in New Issue