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MIPS: Oprofile: Loongson: Unify macro for setting events
Unified macro for counter0 and counter1 to set the event in the control register. This will be needed by Perf. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 4 additions and 4 deletions
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@ -24,8 +24,8 @@
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*/
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#define LOONGSON2_CPU_TYPE "mips/loongson2"
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#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
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#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
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#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
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(((event) & 0x0f) << ((idx) ? 9 : 5))
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#define LOONGSON2_PERFCNT_EXL (1UL << 0)
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#define LOONGSON2_PERFCNT_KERNEL (1UL << 1)
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@ -60,12 +60,12 @@ static void loongson2_reg_setup(struct op_counter_config *cfg)
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/* Compute the performance counter ctrl word. */
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/* For now count kernel and user mode */
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if (cfg[0].enabled) {
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ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event);
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ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
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reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
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}
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if (cfg[1].enabled) {
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ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event);
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ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
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reg.reset_counter2 = (0x80000000ULL - cfg[1].count);
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}
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