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phy: qcom-qmp: Add support for SDX55 QMP PHY
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 83 additions and 0 deletions
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@ -1974,6 +1974,53 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
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};
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static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
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};
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static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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/* phy-type - PCIE/UFS/USB */
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@ -2183,6 +2230,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = {
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"ref", "ref_aux",
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};
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/* usb3 phy on sdx55 doesn't have com_aux clock */
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static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
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"aux", "cfg_ahb", "ref"
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};
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/* list of resets */
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static const char * const msm8996_pciephy_reset_l[] = {
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"phy", "common", "cfg",
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@ -2824,6 +2876,34 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
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.tx_tbl = sdx55_usb3_uniphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
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.rx_tbl = sdx55_usb3_uniphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
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.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
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.clk_list = qmp_v4_sdx55_usbphy_clk_l,
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.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = qmp_v4_usb3_uniphy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static void qcom_qmp_phy_configure_lane(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -4173,6 +4253,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
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.data = &sm8250_qmp_gen3x2_pciephy_cfg,
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}, {
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.compatible = "qcom,sdx55-qmp-usb3-uni-phy",
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.data = &sdx55_usb3_uniphy_cfg,
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},
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{ },
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};
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