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ARM: imx: rename imx6q_set_int_mem_clk_lpm() function
Let's rename the function imx6q_set_int_mem_clk_lpm() to imx6_set_int_mem_clk_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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29b4817d40
commit
8765caa5cb
3 changed files with 6 additions and 6 deletions
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@ -109,7 +109,7 @@ void imx_anatop_init(void);
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void imx_anatop_pre_suspend(void);
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void imx_anatop_post_resume(void);
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int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
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void imx6q_set_int_mem_clk_lpm(bool enable);
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void imx6_set_int_mem_clk_lpm(bool enable);
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void imx6sl_set_wait_clk(bool enter);
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int imx_mmdc_get_ddr_type(void);
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@ -85,7 +85,7 @@ EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused);
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int __init imx6q_cpuidle_init(void)
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{
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/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
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imx6q_set_int_mem_clk_lpm(true);
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imx6_set_int_mem_clk_lpm(true);
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return cpuidle_register(&imx6q_cpuidle_driver, NULL);
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}
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@ -217,7 +217,7 @@ struct imx6_cpu_pm_info {
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u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
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} __aligned(8);
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void imx6q_set_int_mem_clk_lpm(bool enable)
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void imx6_set_int_mem_clk_lpm(bool enable)
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{
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u32 val = readl_relaxed(ccm_base + CGPR);
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@ -367,7 +367,7 @@ static int imx6q_pm_enter(suspend_state_t state)
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switch (state) {
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case PM_SUSPEND_STANDBY:
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imx6_set_lpm(STOP_POWER_ON);
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imx6q_set_int_mem_clk_lpm(true);
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imx6_set_int_mem_clk_lpm(true);
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imx_gpc_pre_suspend(false);
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if (cpu_is_imx6sl())
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imx6sl_set_wait_clk(true);
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@ -380,7 +380,7 @@ static int imx6q_pm_enter(suspend_state_t state)
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break;
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case PM_SUSPEND_MEM:
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imx6_set_lpm(STOP_POWER_OFF);
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imx6q_set_int_mem_clk_lpm(false);
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imx6_set_int_mem_clk_lpm(false);
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imx6q_enable_wb(true);
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/*
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* For suspend into ocram, asm code already take care of
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@ -398,7 +398,7 @@ static int imx6q_pm_enter(suspend_state_t state)
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imx_gpc_post_resume();
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imx6_enable_rbc(false);
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imx6q_enable_wb(false);
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imx6q_set_int_mem_clk_lpm(true);
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imx6_set_int_mem_clk_lpm(true);
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imx6_set_lpm(WAIT_CLOCKED);
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break;
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default:
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