ARM: 8706/1: NOMMU: Move out MPU setup in separate module
Having MPU handling code in dedicated module makes it easier to enhance/maintain it. Tested-by: Szemző András <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin
Russell King
parent
59b6359dd9
commit
877ec119db
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@ -1,8 +1,6 @@
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#ifndef __ARM_MPU_H
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#define __ARM_MPU_H
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#ifdef CONFIG_ARM_MPU
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/* MPUIR layout */
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#define MPUIR_nU 1
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#define MPUIR_DREGION 8
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@ -69,8 +67,18 @@ struct mpu_rgn_info {
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};
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extern struct mpu_rgn_info mpu_rgn_info;
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#ifdef CONFIG_ARM_MPU
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extern void __init adjust_lowmem_bounds_mpu(void);
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extern void __init mpu_setup(void);
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#else
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static inline void adjust_lowmem_bounds_mpu(void) {}
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static inline void mpu_setup(void) {}
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#endif /* !CONFIG_ARM_MPU */
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARM_MPU */
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#endif
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@ -9,6 +9,7 @@ obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
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ifneq ($(CONFIG_MMU),y)
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obj-y += nommu.o
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obj-$(CONFIG_ARM_MPU) += pmsa-v7.o
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endif
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obj-$(CONFIG_ARM_PTDUMP) += dump.o
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@ -27,259 +27,7 @@ unsigned long vectors_base;
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#ifdef CONFIG_ARM_MPU
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struct mpu_rgn_info mpu_rgn_info;
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/* Region number */
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static void rgnr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static void dracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
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}
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/* Region size register */
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static void drsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
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}
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/* Region base address register */
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static void drbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
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}
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static u32 drbar_read(void)
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{
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u32 v;
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asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
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return v;
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}
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/* Optional instruction-side region attributes */
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/* I-side Region access control register */
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static void iracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
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}
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/* I-side Region size register */
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static void irsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
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}
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/* I-side Region base address register */
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static void irbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
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}
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static unsigned long irbar_read(void)
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{
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unsigned long v;
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asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
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return v;
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}
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/* MPU initialisation functions */
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void __init adjust_lowmem_bounds_mpu(void)
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{
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phys_addr_t phys_offset = PHYS_OFFSET;
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phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
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struct memblock_region *reg;
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bool first = true;
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phys_addr_t mem_start;
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phys_addr_t mem_end;
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for_each_memblock(memory, reg) {
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if (first) {
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/*
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* Initially only use memory continuous from
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* PHYS_OFFSET */
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if (reg->base != phys_offset)
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panic("First memory bank must be contiguous from PHYS_OFFSET");
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mem_start = reg->base;
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mem_end = reg->base + reg->size;
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specified_mem_size = reg->size;
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first = false;
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} else {
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/*
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* memblock auto merges contiguous blocks, remove
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* all blocks afterwards in one go (we can't remove
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* blocks separately while iterating)
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*/
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pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
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&mem_end, ®->base);
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memblock_remove(reg->base, 0 - reg->base);
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break;
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}
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}
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/*
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* MPU has curious alignment requirements: Size must be power of 2, and
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* region start must be aligned to the region size
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*/
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if (phys_offset != 0)
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pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
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/*
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* Maximum aligned region might overflow phys_addr_t if phys_offset is
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* 0. Hence we keep everything below 4G until we take the smaller of
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* the aligned_region_size and rounded_mem_size, one of which is
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* guaranteed to be smaller than the maximum physical address.
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*/
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aligned_region_size = (phys_offset - 1) ^ (phys_offset);
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/* Find the max power-of-two sized region that fits inside our bank */
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rounded_mem_size = (1 << __fls(specified_mem_size)) - 1;
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/* The actual region size is the smaller of the two */
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aligned_region_size = aligned_region_size < rounded_mem_size
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? aligned_region_size + 1
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: rounded_mem_size + 1;
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if (aligned_region_size != specified_mem_size) {
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pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
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&specified_mem_size, &aligned_region_size);
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memblock_remove(mem_start + aligned_region_size,
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specified_mem_size - aligned_region_size);
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mem_end = mem_start + aligned_region_size;
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}
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pr_debug("MPU Region from %pa size %pa (end %pa))\n",
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&phys_offset, &aligned_region_size, &mem_end);
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}
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static int mpu_present(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
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}
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static int mpu_max_regions(void)
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{
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/*
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* We don't support a different number of I/D side regions so if we
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* have separate instruction and data memory maps then return
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* whichever side has a smaller number of supported regions.
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*/
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u32 dregions, iregions, mpuir;
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mpuir = read_cpuid(CPUID_MPUIR);
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dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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/* Check for separate d-side and i-side memory maps */
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if (mpuir & MPUIR_nU)
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iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
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/* Use the smallest of the two maxima */
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return min(dregions, iregions);
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}
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static int mpu_iside_independent(void)
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{
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/* MPUIR.nU specifies whether there is *not* a unified memory map */
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return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
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}
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static int mpu_min_region_order(void)
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{
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u32 drbar_result, irbar_result;
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/* We've kept a region free for this probing */
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rgnr_write(MPU_PROBE_REGION);
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isb();
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/*
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* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
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* region order
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*/
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drbar_write(0xFFFFFFFC);
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drbar_result = irbar_result = drbar_read();
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drbar_write(0x0);
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/* If the MPU is non-unified, we use the larger of the two minima*/
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if (mpu_iside_independent()) {
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irbar_write(0xFFFFFFFC);
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irbar_result = irbar_read();
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irbar_write(0x0);
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}
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isb(); /* Ensure that MPU region operations have completed */
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/* Return whichever result is larger */
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return __ffs(max(drbar_result, irbar_result));
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}
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static int mpu_setup_region(unsigned int number, phys_addr_t start,
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unsigned int size_order, unsigned int properties)
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{
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u32 size_data;
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/* We kept a region free for probing resolution of MPU regions*/
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if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
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return -ENOENT;
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if (size_order > 32)
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return -ENOMEM;
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if (size_order < mpu_min_region_order())
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return -ENOMEM;
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/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
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size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
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dsb(); /* Ensure all previous data accesses occur with old mappings */
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rgnr_write(number);
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isb();
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drbar_write(start);
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dracr_write(properties);
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isb(); /* Propagate properties before enabling region */
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drsr_write(size_data);
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/* Check for independent I-side registers */
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if (mpu_iside_independent()) {
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irbar_write(start);
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iracr_write(properties);
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isb();
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irsr_write(size_data);
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}
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isb();
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/* Store region info (we treat i/d side the same, so only store d) */
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mpu_rgn_info.rgns[number].dracr = properties;
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mpu_rgn_info.rgns[number].drbar = start;
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mpu_rgn_info.rgns[number].drsr = size_data;
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return 0;
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}
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/*
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* Set up default MPU regions, doing nothing if there is no MPU
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*/
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void __init mpu_setup(void)
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{
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int region_err;
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if (!mpu_present())
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return;
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region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
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ilog2(memblock.memory.regions[0].size),
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MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
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if (region_err) {
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panic("MPU region initialization failure! %d", region_err);
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} else {
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pr_info("Using ARMv7 PMSA Compliant MPU. "
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"Region independence: %s, Max regions: %d\n",
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mpu_iside_independent() ? "Yes" : "No",
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mpu_max_regions());
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}
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}
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#else
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static void adjust_lowmem_bounds_mpu(void) {}
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static void __init mpu_setup(void) {}
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#endif /* CONFIG_ARM_MPU */
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#endif
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#ifdef CONFIG_CPU_CP15
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#ifdef CONFIG_CPU_HIGH_VECTOR
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@ -0,0 +1,262 @@
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/*
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* Based on linux/arch/arm/mm/nommu.c
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*
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* ARM PMSAv7 supporting functions.
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*/
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#include <linux/memblock.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/mpu.h>
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#include "mm.h"
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/* Region number */
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static void rgnr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static void dracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
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}
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/* Region size register */
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static void drsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
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}
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/* Region base address register */
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static void drbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
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}
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static u32 drbar_read(void)
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{
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u32 v;
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asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
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return v;
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}
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/* Optional instruction-side region attributes */
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/* I-side Region access control register */
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static void iracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
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}
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/* I-side Region size register */
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static void irsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
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}
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/* I-side Region base address register */
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static void irbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
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}
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static unsigned long irbar_read(void)
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{
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unsigned long v;
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asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
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return v;
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}
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/* MPU initialisation functions */
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void __init adjust_lowmem_bounds_mpu(void)
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{
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phys_addr_t phys_offset = PHYS_OFFSET;
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phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
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struct memblock_region *reg;
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bool first = true;
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phys_addr_t mem_start;
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phys_addr_t mem_end;
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for_each_memblock(memory, reg) {
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if (first) {
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/*
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* Initially only use memory continuous from
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* PHYS_OFFSET */
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if (reg->base != phys_offset)
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panic("First memory bank must be contiguous from PHYS_OFFSET");
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mem_start = reg->base;
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mem_end = reg->base + reg->size;
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specified_mem_size = reg->size;
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first = false;
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} else {
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/*
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* memblock auto merges contiguous blocks, remove
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* all blocks afterwards in one go (we can't remove
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* blocks separately while iterating)
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*/
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pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
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&mem_end, ®->base);
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memblock_remove(reg->base, 0 - reg->base);
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break;
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}
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}
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/*
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* MPU has curious alignment requirements: Size must be power of 2, and
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* region start must be aligned to the region size
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*/
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if (phys_offset != 0)
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pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
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/*
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* Maximum aligned region might overflow phys_addr_t if phys_offset is
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* 0. Hence we keep everything below 4G until we take the smaller of
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* the aligned_region_size and rounded_mem_size, one of which is
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* guaranteed to be smaller than the maximum physical address.
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*/
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aligned_region_size = (phys_offset - 1) ^ (phys_offset);
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/* Find the max power-of-two sized region that fits inside our bank */
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rounded_mem_size = (1 << __fls(specified_mem_size)) - 1;
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/* The actual region size is the smaller of the two */
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aligned_region_size = aligned_region_size < rounded_mem_size
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? aligned_region_size + 1
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: rounded_mem_size + 1;
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if (aligned_region_size != specified_mem_size) {
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pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
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&specified_mem_size, &aligned_region_size);
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memblock_remove(mem_start + aligned_region_size,
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specified_mem_size - aligned_region_size);
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mem_end = mem_start + aligned_region_size;
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}
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pr_debug("MPU Region from %pa size %pa (end %pa))\n",
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&phys_offset, &aligned_region_size, &mem_end);
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}
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static int mpu_present(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
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}
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static int mpu_max_regions(void)
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{
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/*
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* We don't support a different number of I/D side regions so if we
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* have separate instruction and data memory maps then return
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* whichever side has a smaller number of supported regions.
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*/
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u32 dregions, iregions, mpuir;
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mpuir = read_cpuid(CPUID_MPUIR);
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dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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/* Check for separate d-side and i-side memory maps */
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if (mpuir & MPUIR_nU)
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iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
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/* Use the smallest of the two maxima */
|
||||
return min(dregions, iregions);
|
||||
}
|
||||
|
||||
static int mpu_iside_independent(void)
|
||||
{
|
||||
/* MPUIR.nU specifies whether there is *not* a unified memory map */
|
||||
return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
|
||||
}
|
||||
|
||||
static int mpu_min_region_order(void)
|
||||
{
|
||||
u32 drbar_result, irbar_result;
|
||||
/* We've kept a region free for this probing */
|
||||
rgnr_write(MPU_PROBE_REGION);
|
||||
isb();
|
||||
/*
|
||||
* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
|
||||
* region order
|
||||
*/
|
||||
drbar_write(0xFFFFFFFC);
|
||||
drbar_result = irbar_result = drbar_read();
|
||||
drbar_write(0x0);
|
||||
/* If the MPU is non-unified, we use the larger of the two minima*/
|
||||
if (mpu_iside_independent()) {
|
||||
irbar_write(0xFFFFFFFC);
|
||||
irbar_result = irbar_read();
|
||||
irbar_write(0x0);
|
||||
}
|
||||
isb(); /* Ensure that MPU region operations have completed */
|
||||
/* Return whichever result is larger */
|
||||
return __ffs(max(drbar_result, irbar_result));
|
||||
}
|
||||
|
||||
static int mpu_setup_region(unsigned int number, phys_addr_t start,
|
||||
unsigned int size_order, unsigned int properties)
|
||||
{
|
||||
u32 size_data;
|
||||
|
||||
/* We kept a region free for probing resolution of MPU regions*/
|
||||
if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
|
||||
return -ENOENT;
|
||||
|
||||
if (size_order > 32)
|
||||
return -ENOMEM;
|
||||
|
||||
if (size_order < mpu_min_region_order())
|
||||
return -ENOMEM;
|
||||
|
||||
/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
|
||||
size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
|
||||
|
||||
dsb(); /* Ensure all previous data accesses occur with old mappings */
|
||||
rgnr_write(number);
|
||||
isb();
|
||||
drbar_write(start);
|
||||
dracr_write(properties);
|
||||
isb(); /* Propagate properties before enabling region */
|
||||
drsr_write(size_data);
|
||||
|
||||
/* Check for independent I-side registers */
|
||||
if (mpu_iside_independent()) {
|
||||
irbar_write(start);
|
||||
iracr_write(properties);
|
||||
isb();
|
||||
irsr_write(size_data);
|
||||
}
|
||||
isb();
|
||||
|
||||
/* Store region info (we treat i/d side the same, so only store d) */
|
||||
mpu_rgn_info.rgns[number].dracr = properties;
|
||||
mpu_rgn_info.rgns[number].drbar = start;
|
||||
mpu_rgn_info.rgns[number].drsr = size_data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up default MPU regions, doing nothing if there is no MPU
|
||||
*/
|
||||
void __init mpu_setup(void)
|
||||
{
|
||||
int region_err;
|
||||
if (!mpu_present())
|
||||
return;
|
||||
|
||||
region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
|
||||
ilog2(memblock.memory.regions[0].size),
|
||||
MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
|
||||
if (region_err) {
|
||||
panic("MPU region initialization failure! %d", region_err);
|
||||
} else {
|
||||
pr_info("Using ARMv7 PMSA Compliant MPU. "
|
||||
"Region independence: %s, Max regions: %d\n",
|
||||
mpu_iside_independent() ? "Yes" : "No",
|
||||
mpu_max_regions());
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue