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clock changes for mvebu for v3.18
- correct timer drift caused by SSCG deviation - fix typo in comment -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJUFVIYAAoJEP45WPkGe8Zns1MQAJeD6jSRzNyqc5Hn0Z2+ibGK TQhFcGF2KTySOSnqP7OpdR/LQXaKIb8bcbslfG7FZBXICEVpkHBibf4DoHQtEwoY fx1QB73jio3ks9UGpQgVPFTgysfxHsuL8/RTT6QOeyUU8Z0pyOSjDqWDh7z5ZPjY aaiT9Ckq1KRzSkMGRqeXZgSqR2lPG1UYet49AlLp1QpjR7i7WfQuQ2W07D2YJQfy ault8QKMhNKQ2U8sB69IV/hBpkf6GAKSos8KMAH0+FwxzlfsP5gMTLUyhxFDQ5sA 4d8qYEPTPj4Acw+uSVI8EDlCWMTyMASCi+Tk6eY9wy2j8zPbfuw1IKtsXqVf3eu9 huIkdrcLlVeQNnSEu7M35GLCmNVc0bG2qKQKSvrJhaDmVSP+5fVP7jJdStDHVhC/ GViuJ8SpS147oTV7yL3hh12UNIORsjvjB+MZL7g60bnHyuAEU5Sd0vQBdqcTqBnF VE1qMawGdI6lzulhGJ4j+yz766ut9x1je9DwLtj218pfyg0nvg4ujrxF2yGkYdVE tQahztzH3DaAX+wPoCybM+HFEtXmlX773Q0TkU7XA7XeFTkXUz5b/CY/A6HertCE 4sGNxw2Wn8m6kvMVkFJ4oKN8VEFvu73SOWmq9Hz9apYMVWvwFeDplqt4zUjb7oCa 1Oofky2uBsHpXYa0v9Yi =CGwg -----END PGP SIGNATURE----- Merge tag 'clk-mvebu-3.18' of git://git.infradead.org/linux-mvebu into clk-next clock changes for mvebu for v3.18 - correct timer drift caused by SSCG deviation - fix typo in comment
This commit is contained in:
commit
8791db53a9
4 changed files with 99 additions and 2 deletions
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@ -23,6 +23,7 @@
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*/
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#define SARL 0 /* Low part [0:31] */
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#define SARL_A370_SSCG_ENABLE BIT(10)
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#define SARL_A370_PCLK_FREQ_OPT 11
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#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
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#define SARL_A370_FAB_FREQ_OPT 15
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@ -133,10 +134,17 @@ static void __init a370_get_clk_ratio(
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}
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}
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static bool a370_is_sscg_enabled(void __iomem *sar)
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{
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return !(readl(sar) & SARL_A370_SSCG_ENABLE);
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}
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static const struct coreclk_soc_desc a370_coreclks = {
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.get_tclk_freq = a370_get_tclk_freq,
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.get_cpu_freq = a370_get_cpu_freq,
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.get_clk_ratio = a370_get_clk_ratio,
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.is_sscg_enabled = a370_is_sscg_enabled,
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.fix_sscg_deviation = kirkwood_fix_sscg_deviation,
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.ratios = a370_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
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};
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@ -27,14 +27,14 @@
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* all modified at the same time, and not separately as for the Armada
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* 370 or the Armada XP SoCs.
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*
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* SAR0[21:17] : CPU frequency DDR frequency L2 frequency
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* SAR1[21:17] : CPU frequency DDR frequency L2 frequency
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* 6 = 400 MHz 400 MHz 200 MHz
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* 15 = 600 MHz 600 MHz 300 MHz
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* 21 = 800 MHz 534 MHz 400 MHz
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* 25 = 1000 MHz 500 MHz 500 MHz
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* others reserved.
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*
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* SAR0[22] : TCLK frequency
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* SAR1[22] : TCLK frequency
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* 0 = 166 MHz
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* 1 = 200 MHz
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*/
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@ -26,8 +26,85 @@
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* Core Clocks
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*/
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#define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3)
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#define SSCG_SPREAD_DOWN 0x0
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#define SSCG_SPREAD_UP 0x1
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#define SSCG_SPREAD_CENTRAL 0x2
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#define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF)
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#define SSCG_CONF_HIGH(reg) ((reg) & 0xFF)
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static struct clk_onecell_data clk_data;
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/*
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* This function can be used by the Kirkwood, the Armada 370, the
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* Armada XP and the Armada 375 SoC. The name of the function was
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* chosen following the dt convention: using the first known SoC
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* compatible with it.
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*/
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u32 kirkwood_fix_sscg_deviation(struct device_node *np, u32 system_clk)
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{
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struct device_node *sscg_np = NULL;
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void __iomem *sscg_map;
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u32 sscg_reg;
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s32 low_bound, high_bound;
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u64 freq_swing_half;
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sscg_np = of_find_node_by_name(np, "sscg");
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if (sscg_np == NULL) {
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pr_err("cannot get SSCG register node\n");
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return system_clk;
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}
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sscg_map = of_iomap(sscg_np, 0);
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if (sscg_map == NULL) {
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pr_err("cannot map SSCG register\n");
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goto out;
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}
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sscg_reg = readl(sscg_map);
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high_bound = SSCG_CONF_HIGH(sscg_reg);
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low_bound = SSCG_CONF_LOW(sscg_reg);
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if ((high_bound - low_bound) <= 0)
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goto out;
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/*
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* From Marvell engineer we got the following formula (when
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* this code was written, the datasheet was erroneous)
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* Spread percentage = 1/96 * (H - L) / H
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* H = SSCG_High_Boundary
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* L = SSCG_Low_Boundary
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*
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* As the deviation is half of spread then it lead to the
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* following formula in the code.
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*
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* To avoid an overflow and not lose any significant digit in
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* the same time we have to use a 64 bit integer.
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*/
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freq_swing_half = (((u64)high_bound - (u64)low_bound)
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* (u64)system_clk);
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do_div(freq_swing_half, (2 * 96 * high_bound));
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switch (SSCG_CONF_MODE(sscg_reg)) {
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case SSCG_SPREAD_DOWN:
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system_clk -= freq_swing_half;
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break;
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case SSCG_SPREAD_UP:
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system_clk += freq_swing_half;
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break;
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case SSCG_SPREAD_CENTRAL:
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default:
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break;
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}
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iounmap(sscg_map);
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out:
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of_node_put(sscg_np);
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return system_clk;
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}
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void __init mvebu_coreclk_setup(struct device_node *np,
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const struct coreclk_soc_desc *desc)
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{
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@ -62,6 +139,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
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of_property_read_string_index(np, "clock-output-names", 1,
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&cpuclk_name);
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rate = desc->get_cpu_freq(base);
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if (desc->is_sscg_enabled && desc->fix_sscg_deviation
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&& desc->is_sscg_enabled(base))
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rate = desc->fix_sscg_deviation(np, rate);
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clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
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CLK_IS_ROOT, rate);
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WARN_ON(IS_ERR(clk_data.clks[1]));
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@ -30,6 +30,8 @@ struct coreclk_soc_desc {
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u32 (*get_tclk_freq)(void __iomem *sar);
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u32 (*get_cpu_freq)(void __iomem *sar);
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void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
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bool (*is_sscg_enabled)(void __iomem *sar);
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u32 (*fix_sscg_deviation)(struct device_node *np, u32 system_clk);
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const struct coreclk_ratio *ratios;
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int num_ratios;
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};
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@ -47,4 +49,9 @@ void __init mvebu_coreclk_setup(struct device_node *np,
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void __init mvebu_clk_gating_setup(struct device_node *np,
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const struct clk_gating_soc_desc *desc);
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/*
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* This function is shared among the Kirkwood, Armada 370, Armada XP
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* and Armada 375 SoC
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*/
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u32 kirkwood_fix_sscg_deviation(struct device_node *np, u32 system_clk);
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#endif
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