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powerpc/dt_cpu_ftrs: Add MMA feature
Matrix multiple assist (MMA) is a new feature added to ISAv3.1 and POWER10. Support on powernv can be selected via a firmware CPU device tree feature which enables it via a PCR bit. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200521014341.29095-7-alistair@popple.id.au
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2 changed files with 18 additions and 2 deletions
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@ -481,7 +481,8 @@
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#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
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#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
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#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
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#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
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#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
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#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
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#define PCR_HIGH_BITS (PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
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#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
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#define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
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/*
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/*
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* These bits are used in the function kvmppc_set_arch_compat() to specify and
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* These bits are used in the function kvmppc_set_arch_compat() to specify and
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* determine both the compatibility level which we want to emulate and the
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* determine both the compatibility level which we want to emulate and the
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@ -75,6 +75,7 @@ static struct {
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u64 lpcr_clear;
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u64 lpcr_clear;
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u64 hfscr;
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u64 hfscr;
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u64 fscr;
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u64 fscr;
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u64 pcr;
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} system_registers;
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} system_registers;
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static void (*init_pmu_registers)(void);
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static void (*init_pmu_registers)(void);
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@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
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if (hv_mode) {
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if (hv_mode) {
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_HFSCR, system_registers.hfscr);
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mtspr(SPRN_HFSCR, system_registers.hfscr);
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mtspr(SPRN_PCR, PCR_MASK);
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mtspr(SPRN_PCR, system_registers.pcr);
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}
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}
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mtspr(SPRN_FSCR, system_registers.fscr);
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mtspr(SPRN_FSCR, system_registers.fscr);
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@ -561,6 +562,18 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
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return 1;
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return 1;
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}
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}
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static int __init feat_enable_mma(struct dt_cpu_feature *f)
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{
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u64 pcr;
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feat_enable(f);
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pcr = mfspr(SPRN_PCR);
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pcr &= ~PCR_MMA_DIS;
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mtspr(SPRN_PCR, pcr);
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return 1;
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}
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struct dt_cpu_feature_match {
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struct dt_cpu_feature_match {
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const char *name;
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const char *name;
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int (*enable)(struct dt_cpu_feature *f);
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int (*enable)(struct dt_cpu_feature *f);
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@ -635,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
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{"vector-binary16", feat_enable, 0},
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{"vector-binary16", feat_enable, 0},
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{"wait-v3", feat_enable, 0},
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{"wait-v3", feat_enable, 0},
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{"prefix-instructions", feat_enable, 0},
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{"prefix-instructions", feat_enable, 0},
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{"matrix-multiply-assist", feat_enable_mma, 0},
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};
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};
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static bool __initdata using_dt_cpu_ftrs;
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static bool __initdata using_dt_cpu_ftrs;
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@ -785,6 +799,7 @@ static void __init cpufeatures_setup_finished(void)
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system_registers.lpcr = mfspr(SPRN_LPCR);
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system_registers.lpcr = mfspr(SPRN_LPCR);
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system_registers.hfscr = mfspr(SPRN_HFSCR);
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system_registers.hfscr = mfspr(SPRN_HFSCR);
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system_registers.fscr = mfspr(SPRN_FSCR);
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system_registers.fscr = mfspr(SPRN_FSCR);
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system_registers.pcr = mfspr(SPRN_PCR);
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pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
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pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
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cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
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cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
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