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ASoC: da7218: Remove 32KHz PLL mode from driver
Functionality has been removed in latest silicon variants. This patch removes the feature from the driver to align. Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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29b4817d40
commit
8799af0d82
2 changed files with 3 additions and 11 deletions
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@ -1819,7 +1819,7 @@ static int da7218_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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if (da7218->mclk_rate == freq)
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return 0;
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if (((freq < 2000000) && (freq != 32768)) || (freq > 54000000)) {
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if ((freq < 2000000) || (freq > 54000000)) {
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dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
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freq);
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return -EINVAL;
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@ -1866,11 +1866,8 @@ static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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u32 freq_ref;
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u64 frac_div;
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/* Verify 32KHz, 2MHz - 54MHz MCLK provided, and set input divider */
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if (da7218->mclk_rate == 32768) {
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indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ;
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indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL;
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} else if (da7218->mclk_rate < 2000000) {
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/* Verify 2MHz - 54MHz MCLK provided, and set input divider */
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if (da7218->mclk_rate < 2000000) {
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dev_err(codec->dev, "PLL input clock %d below valid range\n",
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da7218->mclk_rate);
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return -EINVAL;
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@ -1911,9 +1908,6 @@ static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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case DA7218_SYSCLK_PLL_SRM:
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pll_ctrl |= DA7218_PLL_MODE_SRM;
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break;
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case DA7218_SYSCLK_PLL_32KHZ:
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pll_ctrl |= DA7218_PLL_MODE_32KHZ;
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break;
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default:
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dev_err(codec->dev, "Invalid PLL config\n");
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return -EINVAL;
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@ -888,7 +888,6 @@
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#define DA7218_PLL_MODE_BYPASS (0x0 << 6)
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#define DA7218_PLL_MODE_NORMAL (0x1 << 6)
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#define DA7218_PLL_MODE_SRM (0x2 << 6)
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#define DA7218_PLL_MODE_32KHZ (0x3 << 6)
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/* DA7218_PLL_FRAC_TOP = 0x92 */
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#define DA7218_PLL_FBDIV_FRAC_TOP_SHIFT 0
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@ -1371,7 +1370,6 @@ enum da7218_sys_clk {
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DA7218_SYSCLK_MCLK = 0,
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DA7218_SYSCLK_PLL,
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DA7218_SYSCLK_PLL_SRM,
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DA7218_SYSCLK_PLL_32KHZ
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};
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enum da7218_dev_id {
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