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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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i.MX drivers update for 5.17:
- A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add i.MX8MN display related domain support. - Add optional continuous burst clock support for imx-weim bus driver. - Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and MIX domain. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmG9dygUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM7+jwgAle7/Po7Qs0JVrUwkJOWAjNxveXjv keEC5o+svPOLIToX1lA+bY2CKlok2n6IIiEkpbgc+C+prTip0zJnJUFFHxuOeMkl +/EWTthCAddLwXCdmU6c5HSw8XJ9rkH3YDvd46GkPnZuUiZVVmTYkuZQ25qCbPpE f1kCg2RNVruZAOYHmMsoU+WMH3q40dvGSDVXbcHpNZ19qHooUyk/4jcXGlBJKXDo iGosWLdqMy0vbK4cWFzorPFyTpaF1qq/o7AppfexT1h0f6aLnuKnBA5JXY4y4bvd e+6EZ0VwvtdZBqMNaZLHqltCVA/Y0q2gXGryKUM6n7mGdv/LYictLHPudA== =WKrF -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAjj4ACgkQmmx57+YA GNlesQ/9HT8YKAUTsFRYbzKaK0tduZX9eFS8kIF6NlhTqD5IIYhwG4zZGhezRBdM Xt1DztCKqI5/okIn5mtHa/nPOoXd8mElivqt+z/rNIvdB+QkeVbCAOQvHUXeNS1F +sy8PTHLLGZNOGWGzKB4bFtJnc6yawwjz4EukG59cnC+AUePdo3DTT7Xnhf45j+j SSYdG2wgcQ5OW9okKov+AcoupFosrC3Zcuswf2lPcxOfZY0x6yalXXfmerRUZR+g JKTA3bFVLBG2o7nHcJp9ePh0K03+SfaaT5sSAbFm1DxL4hhtcPQJ2uq7I1kVBWKh 8gBAy5Q+dNNZI/OQxM5TGB3EiQ20qBEdkxDxW2bUwAuG+Qyazgv5gRp5doU7FQnP Kl2f3TkM6/KRJNT3RytesTBSynisC9b4BuzpgFtfCBjK4/LEZSzSG07KHhP+k3pT b0FWQlw9+Rvj/stChWZgVRC6G3ALi7NYf5NLrGhsKjEdrAYBHwoh8OniwI4NyqdK 14qWkPb9ctvh6J1IGQ7c2qG+iXSMc9oogG7dmb9Vas2RI/tMeEOJSWdmEY6TZbSP 40e3Wews2RlU+lT8291Kuq2Dyj0YbK7dZ38ymy9cVHKvixr5QUEHxkJzICcDPqPQ rLdy/VwoSSDqkgNGcdXDdestnEXK7xvhgl/u3zT5RkcxfYxA3Q0= =74GG -----END PGP SIGNATURE----- Merge tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.17: - A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add i.MX8MN display related domain support. - Add optional continuous burst clock support for imx-weim bus driver. - Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and MIX domain. * tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled bus: imx-weim: optionally enable continuous burst clock soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active soc: imx: gpcv2: Synchronously suspend MIX domains Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
87e1287614
4 changed files with 125 additions and 4 deletions
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@ -21,6 +21,7 @@ struct imx_weim_devtype {
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unsigned int cs_stride;
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unsigned int wcr_offset;
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unsigned int wcr_bcm;
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unsigned int wcr_cont_bclk;
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};
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static const struct imx_weim_devtype imx1_weim_devtype = {
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@ -41,6 +42,7 @@ static const struct imx_weim_devtype imx50_weim_devtype = {
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.cs_stride = 0x18,
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.wcr_offset = 0x90,
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.wcr_bcm = BIT(0),
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.wcr_cont_bclk = BIT(3),
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};
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static const struct imx_weim_devtype imx51_weim_devtype = {
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@ -206,8 +208,20 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
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if (devtype->wcr_bcm) {
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reg = readl(base + devtype->wcr_offset);
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writel(reg | devtype->wcr_bcm,
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base + devtype->wcr_offset);
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reg |= devtype->wcr_bcm;
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if (of_property_read_bool(pdev->dev.of_node,
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"fsl,continuous-burst-clk")) {
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if (devtype->wcr_cont_bclk) {
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reg |= devtype->wcr_cont_bclk;
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} else {
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dev_err(&pdev->dev,
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"continuous burst clk not supported.\n");
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return -EINVAL;
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}
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}
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writel(reg, base + devtype->wcr_offset);
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} else {
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dev_err(&pdev->dev, "burst clk mode not supported.\n");
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return -EINVAL;
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@ -377,7 +377,7 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
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}
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}
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pm_runtime_put(domain->dev);
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pm_runtime_put_sync_suspend(domain->dev);
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return 0;
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@ -734,6 +734,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
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.map = IMX8MM_VPUH1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MM_PGC_VPUH1),
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.keep_clocks = true,
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},
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[IMX8MM_POWER_DOMAIN_DISPMIX] = {
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@ -840,6 +841,32 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
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.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
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},
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.pgc = BIT(IMX8MN_PGC_GPUMIX),
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.keep_clocks = true,
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},
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[IMX8MN_POWER_DOMAIN_DISPMIX] = {
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.genpd = {
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.name = "dispmix",
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},
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.bits = {
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.pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
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.map = IMX8MN_DISPMIX_A53_DOMAIN,
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.hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
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.hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
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},
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.pgc = BIT(IMX8MN_PGC_DISPMIX),
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.keep_clocks = true,
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},
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[IMX8MN_POWER_DOMAIN_MIPI] = {
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.genpd = {
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.name = "mipi",
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},
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.bits = {
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.pxx = IMX8MN_MIPI_SW_Pxx_REQ,
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.map = IMX8MN_MIPI_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MN_PGC_MIPI),
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},
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};
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@ -14,6 +14,7 @@
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#include <linux/clk.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#define BLK_SFT_RSTN 0x0
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#define BLK_CLK_EN 0x4
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@ -498,6 +499,77 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
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.num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
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};
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static int imx8mn_disp_power_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
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power_nb);
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if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
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return NOTIFY_OK;
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/* Enable bus clock and deassert bus reset */
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regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
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/*
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* On power up we have no software backchannel to the GPC to
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* wait for the ADB handshake to happen, so we just delay for a
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* bit. On power down the GPC driver waits for the handshake.
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*/
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if (action == GENPD_NOTIFY_ON)
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udelay(5);
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return NOTIFY_OK;
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}
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static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
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[IMX8MN_DISPBLK_PD_MIPI_DSI] = {
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.name = "dispblk-mipi-dsi",
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.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
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.num_clks = 2,
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.gpc_name = "mipi-dsi",
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.rst_mask = BIT(0) | BIT(1),
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.clk_mask = BIT(0) | BIT(1),
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.mipi_phy_rst_mask = BIT(17),
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},
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[IMX8MN_DISPBLK_PD_MIPI_CSI] = {
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.name = "dispblk-mipi-csi",
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.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
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.num_clks = 2,
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.gpc_name = "mipi-csi",
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.rst_mask = BIT(2) | BIT(3),
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.clk_mask = BIT(2) | BIT(3),
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.mipi_phy_rst_mask = BIT(16),
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},
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[IMX8MN_DISPBLK_PD_LCDIF] = {
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.name = "dispblk-lcdif",
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.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
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.num_clks = 3,
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.gpc_name = "lcdif",
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.rst_mask = BIT(4) | BIT(5),
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.clk_mask = BIT(4) | BIT(5),
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},
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[IMX8MN_DISPBLK_PD_ISI] = {
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.name = "dispblk-isi",
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.clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
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"disp_apb_root"},
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.num_clks = 4,
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.gpc_name = "isi",
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.rst_mask = BIT(6) | BIT(7),
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.clk_mask = BIT(6) | BIT(7),
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},
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};
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static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
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.max_reg = 0x84,
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.power_notifier_fn = imx8mn_disp_power_notifier,
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.domains = imx8mn_disp_blk_ctl_domain_data,
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.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
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};
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static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
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{
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.compatible = "fsl,imx8mm-vpu-blk-ctrl",
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@ -505,7 +577,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
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}, {
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.compatible = "fsl,imx8mm-disp-blk-ctrl",
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.data = &imx8mm_disp_blk_ctl_dev_data
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} ,{
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}, {
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.compatible = "fsl,imx8mn-disp-blk-ctrl",
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.data = &imx8mn_disp_blk_ctl_dev_data
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}, {
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/* Sentinel */
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}
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};
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@ -12,4 +12,9 @@
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#define IMX8MN_POWER_DOMAIN_DISPMIX 3
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#define IMX8MN_POWER_DOMAIN_MIPI 4
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#define IMX8MN_DISPBLK_PD_MIPI_DSI 0
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#define IMX8MN_DISPBLK_PD_MIPI_CSI 1
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#define IMX8MN_DISPBLK_PD_LCDIF 2
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#define IMX8MN_DISPBLK_PD_ISI 3
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#endif
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