ASoC: mcasp: Fix implicit BLCK divider setting

The implicit BLCK divider setting was broken by "ASoC: mcasp: don't
override bclk divider if it was provided by the machine"-patch. After
the BCLK divider is implicitly set for the first time the
mcasp->bclk_div gets a non zero value and the implicit setting is
"turned off".

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Jyri Sarha 2014-08-06 16:47:16 +03:00 committed by Mark Brown
parent ae34a78c43
commit 8813543ecb

View file

@ -403,7 +403,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
return ret; return ret;
} }
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
int div, bool explicit)
{ {
struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
@ -420,7 +421,8 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
ACLKXDIV(div - 1), ACLKXDIV_MASK); ACLKXDIV(div - 1), ACLKXDIV_MASK);
mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
ACLKRDIV(div - 1), ACLKRDIV_MASK); ACLKRDIV(div - 1), ACLKRDIV_MASK);
mcasp->bclk_div = div; if (explicit)
mcasp->bclk_div = div;
break; break;
case 2: /* BCLK/LRCLK ratio */ case 2: /* BCLK/LRCLK ratio */
@ -434,6 +436,12 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
return 0; return 0;
} }
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
int div)
{
return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
}
static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir) unsigned int freq, int dir)
{ {
@ -738,7 +746,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
"Inaccurate BCLK: %u Hz / %u != %u Hz\n", "Inaccurate BCLK: %u Hz / %u != %u Hz\n",
mcasp->sysclk_freq, div, bclk_freq); mcasp->sysclk_freq, div, bclk_freq);
} }
davinci_mcasp_set_clkdiv(cpu_dai, 1, div); __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
} }
ret = mcasp_common_hw_param(mcasp, substream->stream, ret = mcasp_common_hw_param(mcasp, substream->stream,