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ASoC: mcasp: Fix implicit BLCK divider setting
The implicit BLCK divider setting was broken by "ASoC: mcasp: don't override bclk divider if it was provided by the machine"-patch. After the BCLK divider is implicitly set for the first time the mcasp->bclk_div gets a non zero value and the implicit setting is "turned off". Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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ae34a78c43
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1 changed files with 11 additions and 3 deletions
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@ -403,7 +403,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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return ret;
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return ret;
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}
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}
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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
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static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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int div, bool explicit)
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{
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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@ -420,7 +421,8 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
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ACLKXDIV(div - 1), ACLKXDIV_MASK);
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ACLKXDIV(div - 1), ACLKXDIV_MASK);
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
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ACLKRDIV(div - 1), ACLKRDIV_MASK);
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ACLKRDIV(div - 1), ACLKRDIV_MASK);
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mcasp->bclk_div = div;
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if (explicit)
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mcasp->bclk_div = div;
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break;
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break;
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case 2: /* BCLK/LRCLK ratio */
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case 2: /* BCLK/LRCLK ratio */
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@ -434,6 +436,12 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
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return 0;
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return 0;
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}
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}
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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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int div)
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{
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return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
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}
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static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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unsigned int freq, int dir)
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{
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{
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@ -738,7 +746,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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"Inaccurate BCLK: %u Hz / %u != %u Hz\n",
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"Inaccurate BCLK: %u Hz / %u != %u Hz\n",
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mcasp->sysclk_freq, div, bclk_freq);
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mcasp->sysclk_freq, div, bclk_freq);
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}
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}
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davinci_mcasp_set_clkdiv(cpu_dai, 1, div);
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__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
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}
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}
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ret = mcasp_common_hw_param(mcasp, substream->stream,
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ret = mcasp_common_hw_param(mcasp, substream->stream,
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