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perf list: Update event description for IBM zEC12/zBC12 to latest level
Update IBM zEC12/zBC12 event counter description to the latest level as described in the documents 1. SA23-2260-07: "The Load-Program-Parameter and the CPU-Measurement Facilities." released on May, 2022 for the following counter sets: * Basic counter set * Problem counter set * Crypto counter set 2. SA23-2261-07: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" released on April 29, 2022 for the following counter sets: * Extended counter set * MT-Diagnostic counter set Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Acked-by: Ian Rogers <irogers@google.com> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Link: https://lore.kernel.org/r/20220531092706.1931503-7-tmricht@linux.ibm.com Cc: acme@kernel.org Cc: gor@linux.ibm.com Cc: hca@linux.ibm.com Cc: svens@linux.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org
This commit is contained in:
Thomas Richter
Arnaldo Carvalho de Melo
parent
dfeab63acd
commit
882f54243a
3 changed files with 89 additions and 89 deletions
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@ -3,84 +3,84 @@
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "0",
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "CPU Cycles",
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"BriefDescription": "Cycle Count",
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"PublicDescription": "Cycle Count"
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"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "1",
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instructions",
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"BriefDescription": "Instruction Count",
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"PublicDescription": "Instruction Count"
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "2",
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"EventCode": "2",
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"EventName": "L1I_DIR_WRITES",
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"EventName": "L1I_DIR_WRITES",
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"BriefDescription": "L1I Directory Writes",
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"BriefDescription": "Level-1 I-Cache Directory Write Count",
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"PublicDescription": "Level-1 I-Cache Directory Write Count"
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "3",
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"EventCode": "3",
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"EventName": "L1I_PENALTY_CYCLES",
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"EventName": "L1I_PENALTY_CYCLES",
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"BriefDescription": "L1I Penalty Cycles",
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "4",
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"EventCode": "4",
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"EventName": "L1D_DIR_WRITES",
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"EventName": "L1D_DIR_WRITES",
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"BriefDescription": "L1D Directory Writes",
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"BriefDescription": "Level-1 D-Cache Directory Write Count",
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"PublicDescription": "Level-1 D-Cache Directory Write Count"
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "5",
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"EventCode": "5",
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"EventName": "L1D_PENALTY_CYCLES",
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"EventName": "L1D_PENALTY_CYCLES",
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"BriefDescription": "L1D Penalty Cycles",
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"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "32",
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"EventCode": "32",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"BriefDescription": "Problem-State CPU Cycles",
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"BriefDescription": "Problem-State Cycle Count",
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"PublicDescription": "Problem-State Cycle Count"
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"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "33",
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"EventCode": "33",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"BriefDescription": "Problem-State Instructions",
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"BriefDescription": "Problem-State Instruction Count",
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"PublicDescription": "Problem-State Instruction Count"
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "34",
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"EventCode": "34",
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"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
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"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
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"BriefDescription": "Problem-State L1I Directory Writes",
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"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
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"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "35",
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"EventCode": "35",
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"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
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"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1I Penalty Cycles",
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
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"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "36",
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"EventCode": "36",
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"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
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"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
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"BriefDescription": "Problem-State L1D Directory Writes",
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"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
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"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "37",
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"EventCode": "37",
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"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
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"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1D Penalty Cycles",
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"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
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"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
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}
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}
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]
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]
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@ -3,112 +3,112 @@
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "64",
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"EventCode": "64",
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"EventName": "PRNG_FUNCTIONS",
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"EventName": "PRNG_FUNCTIONS",
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"BriefDescription": "PRNG Functions",
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"BriefDescription": "PRNG Function Count",
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"PublicDescription": "Total number of the PRNG functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "65",
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"EventCode": "65",
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"EventName": "PRNG_CYCLES",
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"EventName": "PRNG_CYCLES",
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"BriefDescription": "PRNG Cycles",
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"BriefDescription": "PRNG Cycle Count",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "66",
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"EventCode": "66",
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"EventName": "PRNG_BLOCKED_FUNCTIONS",
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"EventName": "PRNG_BLOCKED_FUNCTIONS",
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"BriefDescription": "PRNG Blocked Functions",
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"BriefDescription": "PRNG Blocked Function Count",
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"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "67",
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"EventCode": "67",
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"EventName": "PRNG_BLOCKED_CYCLES",
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"EventName": "PRNG_BLOCKED_CYCLES",
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"BriefDescription": "PRNG Blocked Cycles",
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"BriefDescription": "PRNG Blocked Cycle Count",
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"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "68",
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"EventCode": "68",
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"EventName": "SHA_FUNCTIONS",
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"EventName": "SHA_FUNCTIONS",
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"BriefDescription": "SHA Functions",
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"BriefDescription": "SHA Function Count",
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"PublicDescription": "Total number of SHA functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "69",
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"EventCode": "69",
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"EventName": "SHA_CYCLES",
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"EventName": "SHA_CYCLES",
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"BriefDescription": "SHA Cycles",
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"BriefDescription": "SHA Cycle Count",
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"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "70",
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"EventCode": "70",
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"EventName": "SHA_BLOCKED_FUNCTIONS",
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"EventName": "SHA_BLOCKED_FUNCTIONS",
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"BriefDescription": "SHA Blocked Functions",
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"BriefDescription": "SHA Blocked Function Count",
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"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "71",
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"EventCode": "71",
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"EventName": "SHA_BLOCKED_CYCLES",
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"EventName": "SHA_BLOCKED_CYCLES",
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"BriefDescription": "SHA Bloced Cycles",
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"BriefDescription": "SHA Blocked Cycle Count",
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"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "72",
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"EventCode": "72",
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"EventName": "DEA_FUNCTIONS",
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"EventName": "DEA_FUNCTIONS",
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"BriefDescription": "DEA Functions",
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"BriefDescription": "DEA Function Count",
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"PublicDescription": "Total number of the DEA functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "73",
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"EventCode": "73",
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"EventName": "DEA_CYCLES",
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"EventName": "DEA_CYCLES",
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"BriefDescription": "DEA Cycles",
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"BriefDescription": "DEA Cycle Count",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "74",
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"EventCode": "74",
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"EventName": "DEA_BLOCKED_FUNCTIONS",
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"EventName": "DEA_BLOCKED_FUNCTIONS",
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"BriefDescription": "DEA Blocked Functions",
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"BriefDescription": "DEA Blocked Function Count",
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"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "75",
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"EventCode": "75",
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"EventName": "DEA_BLOCKED_CYCLES",
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"EventName": "DEA_BLOCKED_CYCLES",
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"BriefDescription": "DEA Blocked Cycles",
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"BriefDescription": "DEA Blocked Cycle Count",
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"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "76",
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"EventCode": "76",
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"EventName": "AES_FUNCTIONS",
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"EventName": "AES_FUNCTIONS",
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"BriefDescription": "AES Functions",
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"BriefDescription": "AES Function Count",
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"PublicDescription": "Total number of AES functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of the AES functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "77",
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"EventCode": "77",
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"EventName": "AES_CYCLES",
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"EventName": "AES_CYCLES",
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"BriefDescription": "AES Cycles",
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"BriefDescription": "AES Cycle Count",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "78",
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"EventCode": "78",
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"EventName": "AES_BLOCKED_FUNCTIONS",
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"EventName": "AES_BLOCKED_FUNCTIONS",
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"BriefDescription": "AES Blocked Functions",
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"BriefDescription": "AES Blocked Function Count",
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"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "79",
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"EventCode": "79",
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"EventName": "AES_BLOCKED_CYCLES",
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"EventName": "AES_BLOCKED_CYCLES",
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"BriefDescription": "AES Blocked Cycles",
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"BriefDescription": "AES Blocked Cycle Count",
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"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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}
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}
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]
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]
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"EventCode": "130",
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"EventCode": "130",
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"EventName": "L1D_L2I_SOURCED_WRITES",
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"EventName": "L1D_L2I_SOURCED_WRITES",
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"BriefDescription": "L1D L2I Sourced Writes",
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"BriefDescription": "L1D L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
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},
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},
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{
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{
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"Unit": "CPU-M-CF",
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventCode": "131",
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"EventName": "L1I_L2I_SOURCED_WRITES",
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"EventName": "L1I_L2I_SOURCED_WRITES",
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"BriefDescription": "L1I L2I Sourced Writes",
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"BriefDescription": "L1I L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "132",
|
"EventCode": "132",
|
||||||
"EventName": "L1D_L2D_SOURCED_WRITES",
|
"EventName": "L1D_L2D_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D L2D Sourced Writes",
|
"BriefDescription": "L1D L2D Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "133",
|
"EventCode": "133",
|
||||||
"EventName": "DTLB1_WRITES",
|
"EventName": "DTLB1_WRITES",
|
||||||
"BriefDescription": "DTLB1 Writes",
|
"BriefDescription": "DTLB1 Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "135",
|
"EventCode": "135",
|
||||||
"EventName": "L1D_LMEM_SOURCED_WRITES",
|
"EventName": "L1D_LMEM_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D Local Memory Sourced Writes",
|
"BriefDescription": "L1D Local Memory Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
|
"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "137",
|
"EventCode": "137",
|
||||||
"EventName": "L1I_LMEM_SOURCED_WRITES",
|
"EventName": "L1I_LMEM_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I Local Memory Sourced Writes",
|
"BriefDescription": "L1I Local Memory Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "138",
|
"EventCode": "138",
|
||||||
"EventName": "L1D_RO_EXCL_WRITES",
|
"EventName": "L1D_RO_EXCL_WRITES",
|
||||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
|
"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "139",
|
"EventCode": "139",
|
||||||
"EventName": "DTLB1_HPAGE_WRITES",
|
"EventName": "DTLB1_HPAGE_WRITES",
|
||||||
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
|
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
|
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "140",
|
"EventCode": "140",
|
||||||
"EventName": "ITLB1_WRITES",
|
"EventName": "ITLB1_WRITES",
|
||||||
"BriefDescription": "ITLB1 Writes",
|
"BriefDescription": "ITLB1 Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
|
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "141",
|
"EventCode": "141",
|
||||||
"EventName": "TLB2_PTE_WRITES",
|
"EventName": "TLB2_PTE_WRITES",
|
||||||
"BriefDescription": "TLB2 PTE Writes",
|
"BriefDescription": "TLB2 PTE Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "142",
|
"EventCode": "142",
|
||||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
|
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "143",
|
"EventCode": "143",
|
||||||
"EventName": "TLB2_CRSTE_WRITES",
|
"EventName": "TLB2_CRSTE_WRITES",
|
||||||
"BriefDescription": "TLB2 CRSTE Writes",
|
"BriefDescription": "TLB2 CRSTE Writes",
|
||||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
|
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "144",
|
"EventCode": "144",
|
||||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "145",
|
"EventCode": "145",
|
||||||
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
|
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
|
"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "146",
|
"EventCode": "146",
|
||||||
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
|
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D Off-Book L3 Sourced Writes",
|
"BriefDescription": "L1D Off-Book L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "147",
|
"EventCode": "147",
|
||||||
"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
|
"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D On-Book L4 Sourced Writes",
|
"BriefDescription": "L1D On-Book L4 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "148",
|
"EventCode": "148",
|
||||||
"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
|
"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1D Off-Book L4 Sourced Writes",
|
"BriefDescription": "L1D Off-Book L4 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "149",
|
"EventCode": "149",
|
||||||
"EventName": "TX_NC_TEND",
|
"EventName": "TX_NC_TEND",
|
||||||
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
|
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
|
||||||
"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
|
"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "150",
|
"EventCode": "150",
|
||||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "151",
|
"EventCode": "151",
|
||||||
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
|
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "152",
|
"EventCode": "152",
|
||||||
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
|
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "153",
|
"EventCode": "153",
|
||||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "154",
|
"EventCode": "154",
|
||||||
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
|
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
|
"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "155",
|
"EventCode": "155",
|
||||||
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
|
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I Off-Book L3 Sourced Writes",
|
"BriefDescription": "L1I Off-Book L3 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "156",
|
"EventCode": "156",
|
||||||
"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
|
"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I On-Book L4 Sourced Writes",
|
"BriefDescription": "L1I On-Book L4 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "157",
|
"EventCode": "157",
|
||||||
"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
|
"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
|
||||||
"BriefDescription": "L1I Off-Book L4 Sourced Writes",
|
"BriefDescription": "L1I Off-Book L4 Sourced Writes",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "158",
|
"EventCode": "158",
|
||||||
"EventName": "TX_C_TEND",
|
"EventName": "TX_C_TEND",
|
||||||
"BriefDescription": "Completed TEND instructions in constrained TX mode",
|
"BriefDescription": "Completed TEND instructions in constrained TX mode",
|
||||||
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
|
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "159",
|
"EventCode": "159",
|
||||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "160",
|
"EventCode": "160",
|
||||||
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
|
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "161",
|
"EventCode": "161",
|
||||||
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
|
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
|
||||||
"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
|
"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
|
||||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
|
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "177",
|
"EventCode": "177",
|
||||||
"EventName": "TX_NC_TABORT",
|
"EventName": "TX_NC_TABORT",
|
||||||
"BriefDescription": "Aborted transactions in non-constrained TX mode",
|
"BriefDescription": "Aborted transactions in non-constrained TX mode",
|
||||||
"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
|
"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "178",
|
"EventCode": "178",
|
||||||
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
||||||
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
|
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
|
||||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
|
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Unit": "CPU-M-CF",
|
"Unit": "CPU-M-CF",
|
||||||
"EventCode": "179",
|
"EventCode": "179",
|
||||||
"EventName": "TX_C_TABORT_SPECIAL",
|
"EventName": "TX_C_TABORT_SPECIAL",
|
||||||
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
|
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue