MIPS: JZ4740: use Ingenic SoC UART driver

Remove the serial support from arch/mips/jz4740 & make use of the new
Ingenic SoC UART driver. This is done for both regular & early console
output.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Apelete Seketeli <apelete@seketeli.net>
Cc: Alexandre Courbot <gnurou@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10160/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2015-05-24 16:11:45 +01:00 committed by Ralf Baechle
parent 0cf985f487
commit 8838245d76
11 changed files with 28 additions and 120 deletions

View File

@ -297,7 +297,6 @@ config MACH_INGENIC
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select ARCH_REQUIRE_GPIOLIB
select SYS_HAS_EARLY_PRINTK
select COMMON_CLK
select GENERIC_IRQ_CHIP
select BUILTIN_DTB

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@ -43,4 +43,26 @@
#clock-cells = <1>;
};
uart0: serial@10030000 {
compatible = "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
interrupt-parent = <&intc>;
interrupts = <9>;
clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
clock-names = "baud", "module";
};
uart1: serial@10031000 {
compatible = "ingenic,jz4740-uart";
reg = <0x10031000 0x100>;
interrupt-parent = <&intc>;
interrupts = <8>;
clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
clock-names = "baud", "module";
};
};

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@ -4,6 +4,10 @@
/ {
compatible = "qi,lb60", "ingenic,jz4740";
chosen {
stdout-path = &uart0;
};
};
&ext {

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@ -66,6 +66,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_INGENIC=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_GPIO=y

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@ -35,6 +35,4 @@ extern struct platform_device jz4740_wdt_device;
extern struct platform_device jz4740_pwm_device;
extern struct platform_device jz4740_dma_device;
void jz4740_serial_device_register(void);
#endif

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@ -5,7 +5,7 @@
# Object file lists.
obj-y += prom.o time.o reset.o setup.o \
gpio.o platform.o timer.o serial.o
gpio.o platform.o timer.o
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt

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@ -482,8 +482,6 @@ static int __init qi_lb60_init_platform_devices(void)
gpiod_add_lookup_table(&qi_lb60_audio_gpio_table);
gpiod_add_lookup_table(&qi_lb60_nand_gpio_table);
jz4740_serial_device_register();
spi_register_board_info(qi_lb60_spi_board_info,
ARRAY_SIZE(qi_lb60_spi_board_info));

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@ -30,7 +30,6 @@
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include "serial.h"
#include "clock.h"
/* OHCI controller */
@ -280,50 +279,6 @@ struct platform_device jz4740_adc_device = {
.resource = jz4740_adc_resources,
};
/* Serial */
#define JZ4740_UART_DATA(_id) \
{ \
.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
.iotype = UPIO_MEM, \
.regshift = 2, \
.serial_out = jz4740_serial_out, \
.type = PORT_16550, \
.mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
.irq = JZ4740_IRQ_UART ## _id, \
}
static struct plat_serial8250_port jz4740_uart_data[] = {
JZ4740_UART_DATA(0),
JZ4740_UART_DATA(1),
{},
};
static struct platform_device jz4740_uart_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = jz4740_uart_data,
},
};
void jz4740_serial_device_register(void)
{
struct plat_serial8250_port *p;
struct clk *ext_clk;
unsigned long ext_rate;
ext_clk = clk_get(NULL, "ext");
if (IS_ERR(ext_clk))
panic("unable to get ext clock");
ext_rate = clk_get_rate(ext_clk);
clk_put(ext_clk);
for (p = jz4740_uart_data; p->flags != 0; ++p)
p->uartclk = ext_rate;
platform_device_register(&jz4740_uart_device);
}
/* Watchdog */
static struct resource jz4740_wdt_resources[] = {
{

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@ -53,16 +53,3 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
void prom_putchar(char c)
{
uint8_t lsr;
do {
lsr = readb(UART_REG(UART_LSR));
} while ((lsr & UART_LSR_TEMT) == 0);
writeb(c, UART_REG(UART_TX));
}

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@ -1,33 +0,0 @@
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 serial support
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/io.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
void jz4740_serial_out(struct uart_port *p, int offset, int value)
{
switch (offset) {
case UART_FCR:
value |= 0x10; /* Enable uart module */
break;
case UART_IER:
value |= (value & 0x4) << 2;
break;
default:
break;
}
writeb(value, p->membase + (offset << p->regshift));
}

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@ -1,23 +0,0 @@
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 serial support
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MIPS_JZ4740_SERIAL_H__
#define __MIPS_JZ4740_SERIAL_H__
struct uart_port;
void jz4740_serial_out(struct uart_port *p, int offset, int value);
#endif