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m68knommu: add support for Coldfire 547x/548x interrupt controller
The Coldfire MCF547x/MCF548x have the same interrupt controller as the MCF528x e.g., but only one, not two as in the MCF528x. Modify intc-2.c to support only one interrupt controller if MCFICM_INTC1 is not defined. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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1 changed files with 33 additions and 9 deletions
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@ -1,9 +1,11 @@
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/*
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* intc-2.c
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*
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* General interrupt controller code for the many ColdFire version 2 cores
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* that use the two region INTC interrupt controller. This includes the
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* 523x family, 5270, 5271, 5274, 5275, and the 528x families.
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* General interrupt controller code for the many ColdFire cores that use
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* interrupt controllers with 63 interrupt sources, organized as 56 fully-
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* programmable + 7 fixed-level interrupt sources. This includes the 523x
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* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
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* controllers, and the 547x and 548x families which have only one of them.
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*
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* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
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*
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@ -23,21 +25,37 @@
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#include <asm/traps.h>
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/*
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* Each vector needs a unique priority and level asscoiated with it.
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* We don't really care so much what they are, we don't rely on the
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* tranditional priority interrupt scheme of the m68k/ColdFire.
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* Bit definitions for the ICR family of registers.
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*/
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static u8 intc_intpri = 0x36;
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#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
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#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
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/*
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* Each vector needs a unique priority and level associated with it.
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* We don't really care so much what they are, we don't rely on the
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* traditional priority interrupt scheme of the m68k/ColdFire.
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*/
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static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
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#ifdef MCFICM_INTC1
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#define NR_VECS 128
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#else
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#define NR_VECS 64
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#endif
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static void intc_irq_mask(unsigned int irq)
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{
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
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unsigned long imraddr;
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u32 val, imrbit;
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irq -= MCFINT_VECBASE;
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imraddr = MCF_IPSBAR;
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#ifdef MCFICM_INTC1
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imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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#else
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imraddr += MCFICM_INTC0;
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#endif
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imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
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imrbit = 0x1 << (irq & 0x1f);
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@ -48,13 +66,17 @@ static void intc_irq_mask(unsigned int irq)
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static void intc_irq_unmask(unsigned int irq)
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{
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
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unsigned long intaddr, imraddr, icraddr;
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u32 val, imrbit;
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irq -= MCFINT_VECBASE;
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intaddr = MCF_IPSBAR;
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#ifdef MCFICM_INTC1
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intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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#else
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intaddr += MCFICM_INTC0;
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#endif
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imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
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icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
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imrbit = 0x1 << (irq & 0x1f);
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@ -85,7 +107,9 @@ void __init init_IRQ(void)
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/* Mask all interrupt sources */
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__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
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#ifdef MCFICM_INTC1
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__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
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#endif
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for (irq = 0; (irq < NR_IRQS); irq++) {
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irq_desc[irq].status = IRQ_DISABLED;
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