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ixgbe: enable relaxed ordering for SPARC
This patch makes sure that relaxed ordering is not disabled when on SPARC, where it helps with performance. CC: <kernel-team@fb.com> CC: Sowmini Varadhan <sowmini.varadhan@oracle.com> Reported-by: Sowmini Varadhan <sowmini.varadhan@oracle.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
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parent
bc035fc55e
commit
887012e80a
2 changed files with 12 additions and 4 deletions
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@ -171,17 +171,21 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
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* @hw: pointer to hardware structure
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* @hw: pointer to hardware structure
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*
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*
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* Starts the hardware using the generic start_hw function.
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* Starts the hardware using the generic start_hw function.
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* Disables relaxed ordering Then set pcie completion timeout
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* Disables relaxed ordering for archs other than SPARC
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* Then set pcie completion timeout
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*
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*
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**/
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**/
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static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
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static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
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{
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{
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#ifndef CONFIG_SPARC
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u32 regval;
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u32 regval;
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u32 i;
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u32 i;
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#endif
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s32 ret_val;
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s32 ret_val;
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ret_val = ixgbe_start_hw_generic(hw);
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ret_val = ixgbe_start_hw_generic(hw);
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#ifndef CONFIG_SPARC
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/* Disable relaxed ordering */
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/* Disable relaxed ordering */
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for (i = 0; ((i < hw->mac.max_tx_queues) &&
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for (i = 0; ((i < hw->mac.max_tx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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@ -197,7 +201,7 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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}
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}
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#endif
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if (ret_val)
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if (ret_val)
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return ret_val;
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return ret_val;
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@ -312,7 +312,6 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
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s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
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s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
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{
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{
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u32 i;
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u32 i;
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u32 regval;
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/* Clear the rate limiters */
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/* Clear the rate limiters */
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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@ -321,20 +320,25 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
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}
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}
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IXGBE_WRITE_FLUSH(hw);
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IXGBE_WRITE_FLUSH(hw);
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#ifndef CONFIG_SPARC
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/* Disable relaxed ordering */
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/* Disable relaxed ordering */
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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u32 regval;
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
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regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
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regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
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}
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}
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for (i = 0; i < hw->mac.max_rx_queues; i++) {
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for (i = 0; i < hw->mac.max_rx_queues; i++) {
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u32 regval;
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
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regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
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regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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}
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}
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#endif
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return 0;
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return 0;
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}
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}
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