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accel/habanalabs: handle f/w reserved dram space request
It is possible for FW to request reserved space in dram. If the device supports this option, it will retrieve the size from the f/w and will reserve it. Currently we add the common code infrastructure to support it. Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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3 changed files with 14 additions and 0 deletions
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@ -2783,6 +2783,11 @@ static int hl_fw_dynamic_init_cpu(struct hl_device *hdev,
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hdev->decoder_binning, hdev->rotator_binning);
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}
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if (hdev->asic_prop.support_dynamic_resereved_fw_size) {
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hdev->asic_prop.reserved_fw_mem_size =
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le32_to_cpu(fw_loader->dynamic_loader.comm_desc.rsvd_mem_size_mb);
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}
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return 0;
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}
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@ -641,6 +641,7 @@ struct hl_hints_range {
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* @glbl_err_cause_num: global err cause number.
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* @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is
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* not supported.
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* @reserved_fw_mem_size: size in MB of dram memory reserved for FW.
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* @collective_first_sob: first sync object available for collective use
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* @collective_first_mon: first monitor available for collective use
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* @sync_stream_first_sob: first sync object available for sync stream use
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@ -689,6 +690,7 @@ struct hl_hints_range {
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* @dma_mask: the dma mask to be set for this device
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* @supports_advanced_cpucp_rc: true if new cpucp opcodes are supported.
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* @supports_engine_modes: true if changing engines/engine_cores modes is supported.
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* @support_dynamic_resereved_fw_size: true if we support dynamic reserved size for fw.
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*/
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struct asic_fixed_properties {
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struct hw_queue_properties *hw_queues_props;
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@ -772,6 +774,7 @@ struct asic_fixed_properties {
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u32 num_of_special_blocks;
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u32 glbl_err_cause_num;
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u32 hbw_flush_reg;
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u32 reserved_fw_mem_size;
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u16 collective_first_sob;
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u16 collective_first_mon;
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u16 sync_stream_first_sob;
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@ -808,6 +811,7 @@ struct asic_fixed_properties {
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u8 dma_mask;
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u8 supports_advanced_cpucp_rc;
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u8 supports_engine_modes;
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u8 support_dynamic_resereved_fw_size;
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};
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/**
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@ -570,6 +570,8 @@ struct lkd_fw_comms_desc {
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__le64 img_addr; /* address for next FW component load */
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struct lkd_fw_binning_info binning_info;
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struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
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__le32 rsvd_mem_size_mb; /* reserved memory size [MB] for FW/SVE */
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char reserved1[4];
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};
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enum comms_reset_cause {
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@ -596,6 +598,9 @@ struct lkd_fw_comms_msg {
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__le64 img_addr;
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struct lkd_fw_binning_info binning_info;
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struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
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/* reserved memory size [MB] for FW/SVE */
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__le32 rsvd_mem_size_mb;
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char reserved1[4];
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};
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struct {
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__u8 reset_cause;
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