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[PATCH] x86: cmpxchg improvements
This adjusts i386's cmpxchg patterns so that - for word and long cmpxchg-es the compiler can utilize all possible registers - cmpxchg8b gets disabled when the minimum specified hardware architectur doesn't support it (like was already happening for the byte, word, and long ones). Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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2 changed files with 35 additions and 3 deletions
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@ -424,6 +424,11 @@ config X86_POPAD_OK
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depends on !M386
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depends on !M386
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default y
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default y
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config X86_CMPXCHG64
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bool
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depends on !M386 && !M486
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default y
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config X86_ALIGNMENT_16
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config X86_ALIGNMENT_16
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bool
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bool
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depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
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depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
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@ -167,6 +167,8 @@ struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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#define __xg(x) ((struct __xchg_dummy *)(x))
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#ifdef CONFIG_X86_CMPXCHG64
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/*
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/*
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* there is a loop and the loading of %%eax and %%edx has to
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* there is a loop and the loading of %%eax and %%edx has to
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@ -221,6 +223,8 @@ static inline void __set_64bit_var (unsigned long long *ptr,
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__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
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__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
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__set_64bit(ptr, ll_low(value), ll_high(value)) )
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__set_64bit(ptr, ll_low(value), ll_high(value)) )
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#endif
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/*
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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@ -259,7 +263,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
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#ifdef CONFIG_X86_CMPXCHG
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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#define __HAVE_ARCH_CMPXCHG 1
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#endif
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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unsigned long new, int size)
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@ -275,13 +278,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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case 2:
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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: "memory");
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return prev;
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return prev;
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case 4:
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
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: "=a"(prev)
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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: "memory");
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return prev;
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return prev;
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}
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}
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@ -291,6 +294,30 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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#define cmpxchg(ptr,o,n)\
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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(unsigned long)(n),sizeof(*(ptr))))
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#endif
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#ifdef CONFIG_X86_CMPXCHG64
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static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
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unsigned long long new)
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{
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unsigned long long prev;
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__asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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#define cmpxchg64(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
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(unsigned long long)(n)))
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#endif
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#ifdef __KERNEL__
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#ifdef __KERNEL__
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struct alt_instr {
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struct alt_instr {
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