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drm/i915: Enable per-lane drive settings for icl+

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Now that the link buf_trans, link training, and the
combo/mg/dkl/snps phy programming are all fixed up we can
allow per-lane DP drive settings on icl+. Make it so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-13-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
Ville Syrjälä 2021-10-06 23:49:33 +03:00
parent 3e9cf8f055
commit 88a2441522
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View file

@ -301,7 +301,10 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
DISPLAY_VER(i915) >= 11;
}
/* 128b/132b */