mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 01:41:39 +00:00
irqchip: bcm2836: Move SMP startup code to arch/arm (v2)
In order to easily provide SMP for BCM2837 on 32-bit and 64-bit
the SMP startup code was placed in irq-bcm2836. That's not the
right approach. So move this code where it belongs.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Fixes: 41f4988cc2
("irqchip/bcm2836: Add SMP support for the 2836")
Tested-by: Eric Anholt <eric@anholt.net>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
parent
1d66af8190
commit
88bbe85dcd
6 changed files with 127 additions and 78 deletions
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@ -43,6 +43,11 @@ endif
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# BCM2835
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# BCM2835
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obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
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ifeq ($(CONFIG_ARCH_BCM2835),y)
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ifeq ($(CONFIG_ARM),y)
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obj-$(CONFIG_SMP) += platsmp.o
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endif
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endif
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# BCM5301X
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# BCM5301X
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obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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@ -19,16 +19,20 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/map.h>
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#include "platsmp.h"
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static const char * const bcm2835_compat[] = {
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static const char * const bcm2835_compat[] = {
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#ifdef CONFIG_ARCH_MULTI_V6
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#ifdef CONFIG_ARCH_MULTI_V6
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"brcm,bcm2835",
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"brcm,bcm2835",
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#endif
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#endif
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#ifdef CONFIG_ARCH_MULTI_V7
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#ifdef CONFIG_ARCH_MULTI_V7
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"brcm,bcm2836",
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"brcm,bcm2836",
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"brcm,bcm2837",
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#endif
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#endif
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NULL
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NULL
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};
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};
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DT_MACHINE_START(BCM2835, "BCM2835")
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DT_MACHINE_START(BCM2835, "BCM2835")
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.dt_compat = bcm2835_compat
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.dt_compat = bcm2835_compat,
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.smp = smp_ops(bcm2836_smp_ops),
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MACHINE_END
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MACHINE_END
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@ -17,6 +17,7 @@
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/irqchip/irq-bcm2836.h>
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#include <linux/jiffies.h>
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#include <linux/jiffies.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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@ -287,6 +288,35 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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return ret;
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return ret;
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}
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}
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static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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void __iomem *intc_base;
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struct device_node *dn;
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char *name;
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name = "brcm,bcm2836-l1-intc";
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dn = of_find_compatible_node(NULL, NULL, name);
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if (!dn) {
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pr_err("unable to find intc node\n");
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return -ENODEV;
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}
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intc_base = of_iomap(dn, 0);
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of_node_put(dn);
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if (!intc_base) {
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pr_err("unable to remap intc base register\n");
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return -ENOMEM;
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}
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writel(virt_to_phys(secondary_startup),
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intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
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iounmap(intc_base);
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return 0;
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}
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static const struct smp_operations kona_smp_ops __initconst = {
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static const struct smp_operations kona_smp_ops __initconst = {
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.smp_prepare_cpus = bcm_smp_prepare_cpus,
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.smp_prepare_cpus = bcm_smp_prepare_cpus,
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.smp_boot_secondary = kona_boot_secondary,
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.smp_boot_secondary = kona_boot_secondary,
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@ -305,3 +335,8 @@ static const struct smp_operations nsp_smp_ops __initconst = {
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.smp_boot_secondary = nsp_boot_secondary,
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.smp_boot_secondary = nsp_boot_secondary,
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};
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};
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CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
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CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
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const struct smp_operations bcm2836_smp_ops __initconst = {
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.smp_boot_secondary = bcm2836_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);
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10
arch/arm/mach-bcm/platsmp.h
Normal file
10
arch/arm/mach-bcm/platsmp.h
Normal file
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@ -0,0 +1,10 @@
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/*
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* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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*/
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extern const struct smp_operations bcm2836_smp_ops;
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@ -19,63 +19,10 @@
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#include <linux/of_irq.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/irq-bcm2836.h>
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#include <asm/exception.h>
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#include <asm/exception.h>
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#define LOCAL_CONTROL 0x000
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#define LOCAL_PRESCALER 0x008
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/*
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* The low 2 bits identify the CPU that the GPU IRQ goes to, and the
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* next 2 bits identify the CPU that the GPU FIQ goes to.
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*/
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#define LOCAL_GPU_ROUTING 0x00c
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/* When setting bits 0-3, enables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_SET 0x010
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/* When setting bits 0-3, disables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_CLR 0x014
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/*
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* The low 4 bits of this are the CPU's timer IRQ enables, and the
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* next 4 bits are the CPU's timer FIQ enables (which override the IRQ
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* bits).
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*/
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#define LOCAL_TIMER_INT_CONTROL0 0x040
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/*
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* The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
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* the next 4 bits are the CPU's per-mailbox FIQ enables (which
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* override the IRQ bits).
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*/
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#define LOCAL_MAILBOX_INT_CONTROL0 0x050
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/*
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* The CPU's interrupt status register. Bits are defined by the the
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* LOCAL_IRQ_* bits below.
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*/
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#define LOCAL_IRQ_PENDING0 0x060
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/* Same status bits as above, but for FIQ. */
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#define LOCAL_FIQ_PENDING0 0x070
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/*
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* Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
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* these bits are organized by mailbox number and then CPU number. We
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* use mailbox 0 for IPIs. The mailbox's interrupt is raised while
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* any bit is set.
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*/
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#define LOCAL_MAILBOX0_SET0 0x080
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#define LOCAL_MAILBOX3_SET0 0x08c
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/* Mailbox write-to-clear bits. */
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#define LOCAL_MAILBOX0_CLR0 0x0c0
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#define LOCAL_MAILBOX3_CLR0 0x0cc
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#define LOCAL_IRQ_CNTPSIRQ 0
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#define LOCAL_IRQ_CNTPNSIRQ 1
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#define LOCAL_IRQ_CNTHPIRQ 2
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#define LOCAL_IRQ_CNTVIRQ 3
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#define LOCAL_IRQ_MAILBOX0 4
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#define LOCAL_IRQ_MAILBOX1 5
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#define LOCAL_IRQ_MAILBOX2 6
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#define LOCAL_IRQ_MAILBOX3 7
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#define LOCAL_IRQ_GPU_FAST 8
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#define LOCAL_IRQ_PMU_FAST 9
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#define LAST_IRQ LOCAL_IRQ_PMU_FAST
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struct bcm2836_arm_irqchip_intc {
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struct bcm2836_arm_irqchip_intc {
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struct irq_domain *domain;
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struct irq_domain *domain;
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void __iomem *base;
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void __iomem *base;
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@ -215,24 +162,6 @@ static int bcm2836_cpu_dying(unsigned int cpu)
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cpu);
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cpu);
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_ARM
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static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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unsigned long secondary_startup_phys =
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(unsigned long)virt_to_phys((void *)secondary_startup);
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writel(secondary_startup_phys,
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intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
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return 0;
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}
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static const struct smp_operations bcm2836_smp_ops __initconst = {
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.smp_boot_secondary = bcm2836_smp_boot_secondary,
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};
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#endif
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#endif
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#endif
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static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
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static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
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@ -249,10 +178,6 @@ bcm2836_arm_irqchip_smp_init(void)
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bcm2836_cpu_dying);
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bcm2836_cpu_dying);
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set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
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set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
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#ifdef CONFIG_ARM
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smp_set_ops(&bcm2836_smp_ops);
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#endif
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#endif
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#endif
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}
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}
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70
include/linux/irqchip/irq-bcm2836.h
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70
include/linux/irqchip/irq-bcm2836.h
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@ -0,0 +1,70 @@
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/*
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* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
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*
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* Copyright 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define LOCAL_CONTROL 0x000
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#define LOCAL_PRESCALER 0x008
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/*
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* The low 2 bits identify the CPU that the GPU IRQ goes to, and the
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* next 2 bits identify the CPU that the GPU FIQ goes to.
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*/
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#define LOCAL_GPU_ROUTING 0x00c
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/* When setting bits 0-3, enables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_SET 0x010
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/* When setting bits 0-3, disables PMU interrupts on that CPU. */
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#define LOCAL_PM_ROUTING_CLR 0x014
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/*
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* The low 4 bits of this are the CPU's timer IRQ enables, and the
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* next 4 bits are the CPU's timer FIQ enables (which override the IRQ
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* bits).
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*/
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#define LOCAL_TIMER_INT_CONTROL0 0x040
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/*
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* The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
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* the next 4 bits are the CPU's per-mailbox FIQ enables (which
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* override the IRQ bits).
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*/
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#define LOCAL_MAILBOX_INT_CONTROL0 0x050
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/*
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* The CPU's interrupt status register. Bits are defined by the the
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* LOCAL_IRQ_* bits below.
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*/
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#define LOCAL_IRQ_PENDING0 0x060
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/* Same status bits as above, but for FIQ. */
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#define LOCAL_FIQ_PENDING0 0x070
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/*
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* Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
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* these bits are organized by mailbox number and then CPU number. We
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* use mailbox 0 for IPIs. The mailbox's interrupt is raised while
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* any bit is set.
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*/
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#define LOCAL_MAILBOX0_SET0 0x080
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#define LOCAL_MAILBOX3_SET0 0x08c
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/* Mailbox write-to-clear bits. */
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#define LOCAL_MAILBOX0_CLR0 0x0c0
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#define LOCAL_MAILBOX3_CLR0 0x0cc
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#define LOCAL_IRQ_CNTPSIRQ 0
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#define LOCAL_IRQ_CNTPNSIRQ 1
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#define LOCAL_IRQ_CNTHPIRQ 2
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#define LOCAL_IRQ_CNTVIRQ 3
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#define LOCAL_IRQ_MAILBOX0 4
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#define LOCAL_IRQ_MAILBOX1 5
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#define LOCAL_IRQ_MAILBOX2 6
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#define LOCAL_IRQ_MAILBOX3 7
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#define LOCAL_IRQ_GPU_FAST 8
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#define LOCAL_IRQ_PMU_FAST 9
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#define LAST_IRQ LOCAL_IRQ_PMU_FAST
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